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| author | Paolo Bonzini <pbonzini@redhat.com> | 2024-06-18 09:13:49 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-07-16 18:18:25 +0200 |
| commit | 8b131065080af3cf2dda04e4e190c5a74fec2f31 (patch) | |
| tree | eb484586b33774572eddbfe123be2988e565a054 /include/hw/core/resetcontainer.h | |
| parent | 05d41bbcb34ee30465517229a888da93666b4f3f (diff) | |
| download | focaccia-qemu-8b131065080af3cf2dda04e4e190c5a74fec2f31.tar.gz focaccia-qemu-8b131065080af3cf2dda04e4e190c5a74fec2f31.zip | |
target/i386/tcg: use X86Access for TSS access
This takes care of probing the vaddr range in advance, and is also faster because it avoids repeated TLB lookups. It also matches the Intel manual better, as it says "Checks that the current (old) TSS, new TSS, and all segment descriptors used in the task switch are paged into system memory"; note however that it's not clear how the processor checks for segment descriptors, and this check is not included in the AMD manual. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'include/hw/core/resetcontainer.h')
0 files changed, 0 insertions, 0 deletions