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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-03-07 12:19:03 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-07 12:19:03 +0000 |
| commit | 2808d3b38a5232e263338e1b812bb1f6c2d56bcf (patch) | |
| tree | bdbed0d02bd0305e5c1645eacc0f6fcd7d002ac0 /include/hw/gpio/stm32l4x5_gpio.h | |
| parent | 485eb324e352a53bdf99f90511bd546eebab68f5 (diff) | |
| download | focaccia-qemu-2808d3b38a5232e263338e1b812bb1f6c2d56bcf.tar.gz focaccia-qemu-2808d3b38a5232e263338e1b812bb1f6c2d56bcf.zip | |
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is implemented. This is similar to the existing CNTVOFF_EL2, except that it controls a hypervisor-adjustable offset made to the physical counter and timer. Implement the handling for this register, which includes control/trap bits in SCR_EL3 and CNTHCTL_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/gpio/stm32l4x5_gpio.h')
0 files changed, 0 insertions, 0 deletions