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authorIgor Mammedov <imammedo@redhat.com>2016-06-16 14:23:48 +0200
committerMichael S. Tsirkin <mst@redhat.com>2016-06-24 08:34:47 +0300
commit1f3aba377d2a531453f018c70de2580a142c74c9 (patch)
treef862c951297fd7daf19cf12754fc2f8d9fe6a019 /include/hw/ide/internal.h
parentd8d69e1f51e493e21fa75ce80cfacd002bf8a895 (diff)
downloadfocaccia-qemu-1f3aba377d2a531453f018c70de2580a142c74c9.tar.gz
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pc: acpi: drop intermediate PCMachineState.node_cpu
PCMachineState.node_cpu was used for mapping APIC ID
to numa node id as CPU entries in SRAT used to be
built on sparse APIC ID bitmap (up to apic_id_limit).
However since commit
  5803fce pc: acpi: SRAT: create only valid processor lapic entries
CPU entries in SRAT aren't build using apic bitmap
but using 0..maxcpus index instead which is also used
for creating numa_info[x].node_cpu map.
So instead of doing useless intermediate conversion from
  1. node by cpu index -> node by apic id
       i.e. numa_info[x].node_cpu -> PCMachineState.node_cpu
  2. apic id -> srat entry PMX
       PCMachineState.node_cpu[apic id] -> PMX value
use numa_info[x].node_cpu map directly like ARM does and do
  1. numa_info[x].node_cpu -> PMX value using index
     in range 0..maxcpus
and drop not necessary PCMachineState.node_cpu and related
code.

That also removes the last (not counting legacy hotplug)
dependency of ACPI code on apic_id_limit and need to allocate
huge sparse PCMachineState.node_cpu array in case of 32-bit
APIC IDs.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/ide/internal.h')
0 files changed, 0 insertions, 0 deletions