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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-03-07 11:59:21 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-03-09 14:36:53 +0100 |
| commit | 35c909cd80d4095690bb1c98c263b01d9617de65 (patch) | |
| tree | 48737cc97d615b0534e29c2489ced2d0c390e06f /include/hw/intc/aspeed_intc.h | |
| parent | 63f3618f9be0f28ff36cd4b5685877715b97e669 (diff) | |
| download | focaccia-qemu-35c909cd80d4095690bb1c98c263b01d9617de65.tar.gz focaccia-qemu-35c909cd80d4095690bb1c98c263b01d9617de65.zip | |
hw/intc/aspeed: Add support for multiple output pins in INTC
Added support for multiple output pins in the INTC controller to accommodate the AST2700 A1. Introduced "num_outpins" to represent the number of output pins. Updated the IRQ handling logic to initialize and connect output pins separately from input pins. Modified the "aspeed_soc_ast2700_realize" function to connect source orgates to INTC and INTC to GIC128 - GIC136. Updated the "aspeed_intc_realize" function to initialize output pins. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-13-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to '')
| -rw-r--r-- | include/hw/intc/aspeed_intc.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 58be5b3e13..2a22e30846 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -16,8 +16,8 @@ #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) -#define ASPEED_INTC_NR_INTS 9 #define ASPEED_INTC_MAX_INPINS 9 +#define ASPEED_INTC_MAX_OUTPINS 9 struct AspeedINTCState { /*< private >*/ @@ -29,7 +29,7 @@ struct AspeedINTCState { uint32_t *regs; OrIRQState orgates[ASPEED_INTC_MAX_INPINS]; - qemu_irq output_pins[ASPEED_INTC_NR_INTS]; + qemu_irq output_pins[ASPEED_INTC_MAX_OUTPINS]; uint32_t enable[ASPEED_INTC_MAX_INPINS]; uint32_t mask[ASPEED_INTC_MAX_INPINS]; @@ -41,6 +41,7 @@ struct AspeedINTCClass { uint32_t num_lines; uint32_t num_inpins; + uint32_t num_outpins; uint64_t mem_size; uint64_t nr_regs; uint64_t reg_offset; |