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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-08-30 15:34:36 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-09-21 07:56:49 +1000 |
| commit | a714b8aa029c2a6cc0b99a798f4f8b6d4282e711 (patch) | |
| tree | 90c3c011b203b8e9f7d05b473c3b6101c0f2f209 /include/hw/intc/ibex_plic.h | |
| parent | 0f0b70eeecdd4e0f29efe28a7ffec01cbe5c43bf (diff) | |
| download | focaccia-qemu-a714b8aa029c2a6cc0b99a798f4f8b6d4282e711.tar.gz focaccia-qemu-a714b8aa029c2a6cc0b99a798f4f8b6d4282e711.zip | |
hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer and soft MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-id: 946e1ef5e268b24084c7ddad84c146de62a56736.1630301632.git.alistair.francis@wdc.com
Diffstat (limited to 'include/hw/intc/ibex_plic.h')
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