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| author | Bibo Mao <maobibo@loongson.cn> | 2025-05-07 10:31:36 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2025-05-14 15:43:46 +0800 |
| commit | c2658b0de5cb24b6eb49751c92380d30f1d9258f (patch) | |
| tree | d8cbe54a53affdff01e6930980c39daa31177f0c /include/hw/intc/loongarch_pic_common.h | |
| parent | e95e4e818b7821a66c4346761c6f63b93177685a (diff) | |
| download | focaccia-qemu-c2658b0de5cb24b6eb49751c92380d30f1d9258f.tar.gz focaccia-qemu-c2658b0de5cb24b6eb49751c92380d30f1d9258f.zip | |
hw/intc/loongarch_pch: Set version information at initial stage
Register PCH_PIC_INT_ID constains version and supported irq number information, and it is read only register. The detailed value can be set at initial stage, rather than read callback. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20250507023148.1877287-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to 'include/hw/intc/loongarch_pic_common.h')
| -rw-r--r-- | include/hw/intc/loongarch_pic_common.h | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h index 2b4b483c63..7a9a2bdd46 100644 --- a/include/hw/intc/loongarch_pic_common.h +++ b/include/hw/intc/loongarch_pic_common.h @@ -10,9 +10,9 @@ #include "hw/pci-host/ls7a.h" #include "hw/sysbus.h" -#define PCH_PIC_INT_ID_VAL 0x7000000UL -#define PCH_PIC_INT_ID_VER 0x1UL #define PCH_PIC_INT_ID 0x00 +#define PCH_PIC_INT_ID_VAL 0x7 +#define PCH_PIC_INT_ID_VER 0x1 #define PCH_PIC_INT_MASK 0x20 #define PCH_PIC_HTMSI_EN 0x40 #define PCH_PIC_INT_EDGE 0x60 @@ -30,10 +30,23 @@ OBJECT_DECLARE_TYPE(LoongArchPICCommonState, LoongArchPICCommonClass, LOONGARCH_PIC_COMMON) +union LoongArchPIC_ID { + struct { + uint8_t _reserved_0[3]; + uint8_t id; + uint8_t version; + uint8_t _reserved_1; + uint8_t irq_num; + uint8_t _reserved_2; + } QEMU_PACKED desc; + uint64_t data; +}; + struct LoongArchPICCommonState { SysBusDevice parent_obj; qemu_irq parent_irq[64]; + union LoongArchPIC_ID id; /* 0x00 interrupt ID register */ uint64_t int_mask; /* 0x020 interrupt mask register */ uint64_t htmsi_en; /* 0x040 1=msi */ uint64_t intedge; /* 0x060 edge=1 level=0 */ |