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authorPeter Maydell <peter.maydell@linaro.org>2021-02-15 11:51:38 +0000
committerPeter Maydell <peter.maydell@linaro.org>2021-03-08 11:54:16 +0000
commit50b52b18cdb9294ce83dd49bb60b8e55a6526ea0 (patch)
treee42ed8b542b3230027b90669d2610d8495a29953 /include/hw/misc/armsse-cpuid.h
parentced8bb04ae1b41d5aee5a8f782653149fc0b0367 (diff)
downloadfocaccia-qemu-50b52b18cdb9294ce83dd49bb60b8e55a6526ea0.tar.gz
focaccia-qemu-50b52b18cdb9294ce83dd49bb60b8e55a6526ea0.zip
hw/arm/mps2: Update old infocenter.arm.com URLs
Update old infocenter.arm.com URLs to the equivalent developer.arm.com
ones (the old URLs should redirect, but we might as well avoid the
redirection notice, and the new URLs are pleasantly shorter).

This commit covers the links to the MPS2 board TRM, the various
Application Notes, the IoTKit and SSE-200 documents.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-25-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/misc/armsse-cpuid.h')
-rw-r--r--include/hw/misc/armsse-cpuid.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/misc/armsse-cpuid.h b/include/hw/misc/armsse-cpuid.h
index a61355e516..9c0926322c 100644
--- a/include/hw/misc/armsse-cpuid.h
+++ b/include/hw/misc/armsse-cpuid.h
@@ -12,7 +12,7 @@
 /*
  * This is a model of the "CPU_IDENTITY" register block which is part of the
  * Arm SSE-200 and documented in
- * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ * https://developer.arm.com/documentation/101104/latest/
  *
  * QEMU interface:
  *  + QOM property "CPUID": the value to use for the CPUID register