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| author | Kane-Chen-AS <kane_chen@aspeedtech.com> | 2025-08-12 17:40:02 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-09-29 18:00:20 +0200 |
| commit | 8970c95c4db99dd44ff463acc14c69510776cdee (patch) | |
| tree | 348ef3c217d74267f420bcc2124d34a7fdc00c40 /include/hw/misc/aspeed_sbc.h | |
| parent | c6b4279a9240a838632e2d689a138da96545c540 (diff) | |
| download | focaccia-qemu-8970c95c4db99dd44ff463acc14c69510776cdee.tar.gz focaccia-qemu-8970c95c4db99dd44ff463acc14c69510776cdee.zip | |
hw/nvram/aspeed_otp: Add OTP programming semantics and tracing
Implement correct OTP programming behavior for Aspeed OTP: - Support read-modify-write flow with one-way bit programming: * prog_bit uses 0s as the "to-be-programmed" mask. * Even-indexed words: 0->1, odd-indexed words: 1->0. * Reject non-programmable requests and log conflicts. - Enable unaligned accesses in MemoryRegionOps. Since each OTP address maps to a 1DW (4B) or 2DW (8B) block in the backing store, upper-layer accesses may be unaligned to block boundaries. This matches the irreversible, word-parity-dependent programming rules of Aspeed SoCs and exposes changes via QEMU trace events. Signed-off-by: Kane-Chen-AS <kane_chen@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250812094011.2617526-6-kane_chen@aspeedtech.com [ clg: Fixed PRIx64 format in aspeed_otp_write() ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'include/hw/misc/aspeed_sbc.h')
0 files changed, 0 insertions, 0 deletions