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| author | Cédric Le Goater <clg@kaod.org> | 2019-09-25 16:32:32 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-10-15 18:09:04 +0100 |
| commit | fadefada4d07a3a77c4171244cded0e9af81331c (patch) | |
| tree | 0ad3e577ea46c5dd89c86caf669d58d2597c6985 /include/hw/misc/aspeed_scu.h | |
| parent | c20375dd8678eae2462a986938e6d119cb5abefa (diff) | |
| download | focaccia-qemu-fadefada4d07a3a77c4171244cded0e9af81331c.tar.gz focaccia-qemu-fadefada4d07a3a77c4171244cded0e9af81331c.zip | |
aspeed/timer: Add support for IRQ status register on the AST2600
The AST2600 timer replaces control register 2 with a interrupt status register. It is set by hardware when an IRQ occurs and cleared by software. Modify the vmstate version to take into account the new fields. Based on previous work from Joel Stanley. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-8-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw/misc/aspeed_scu.h')
0 files changed, 0 insertions, 0 deletions