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authorBin Meng <bin.meng@windriver.com>2020-09-03 18:40:13 +0800
committerAlistair Francis <alistair.francis@wdc.com>2020-09-09 15:54:19 -0700
commit9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae (patch)
treee43324f5eb23319ff3d718d6617feb86d004ddf9 /include/hw/riscv/sifive_u.h
parent89ece6f76f089bc415fc4b8c78f7dbe74113380c (diff)
downloadfocaccia-qemu-9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae.tar.gz
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hw/riscv: Move sifive_u_prci model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv/sifive_u.h')
-rw-r--r--include/hw/riscv/sifive_u.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 793000a2ed..cbeb2286d7 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -24,8 +24,8 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_prci.h"
 #include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \