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| author | Artyom Tarasenko <atar4qemu@gmail.com> | 2016-11-02 10:37:44 +0100 |
|---|---|---|
| committer | Artyom Tarasenko <atar4qemu@gmail.com> | 2017-01-18 22:03:44 +0100 |
| commit | 3390537b5df4014e24a30f9bdcfa05c2bd0cd6d8 (patch) | |
| tree | 980266b3bcd1df564a797415a1e7ccf5f5b4be56 /include/hw/timer/sun4v-rtc.h | |
| parent | 7285fba083de3f14f6e98abb4469173b56da9480 (diff) | |
| download | focaccia-qemu-3390537b5df4014e24a30f9bdcfa05c2bd0cd6d8.tar.gz focaccia-qemu-3390537b5df4014e24a30f9bdcfa05c2bd0cd6d8.zip | |
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased with Block Initializing Store ASIs. "UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them in the chapter "5.9 Block Initializing Store ASIs" Integer stores of all sizes are allowed with these ASIs. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Diffstat (limited to 'include/hw/timer/sun4v-rtc.h')
0 files changed, 0 insertions, 0 deletions