diff options
| author | Wilfred Mallawa <wilfred.mallawa@wdc.com> | 2022-01-10 15:16:06 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | 28ca4689ae94a27a6a337546425cda30d0e885c3 (patch) | |
| tree | f94b86e92e91f720651dd549a335d33167791616 /include/hw/timer | |
| parent | 2c89b5af5e72ab8c9d544c6e30399528b2238827 (diff) | |
| download | focaccia-qemu-28ca4689ae94a27a6a337546425cda30d0e885c3.tar.gz focaccia-qemu-28ca4689ae94a27a6a337546425cda30d0e885c3.zip | |
hw: timer: ibex_timer: Fixup reading w/o register
This change fixes a bug where a write only register is read. As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table the 'INTR_TEST0' register is write only. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/timer')
| -rw-r--r-- | include/hw/timer/ibex_timer.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.h index b6f69b38ee..1a0a28d5fa 100644 --- a/include/hw/timer/ibex_timer.h +++ b/include/hw/timer/ibex_timer.h @@ -43,7 +43,6 @@ struct IbexTimerState { uint32_t timer_compare_upper0; uint32_t timer_intr_enable; uint32_t timer_intr_state; - uint32_t timer_intr_test; uint32_t timebase_freq; |