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| author | Rajnesh Kanwal <rkanwal@rivosinc.com> | 2025-02-12 10:18:49 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-03-04 15:42:54 +1000 |
| commit | 8b65852196650417532ff924c8a2cb0117e2be19 (patch) | |
| tree | 1bdca070f1da1d4c6e5481f2b8e66d4f1e947faf /include/standard-headers/linux/virtio_pci.h | |
| parent | cb0c4760263d418ea47afa9e6d88944e96e128f1 (diff) | |
| download | focaccia-qemu-8b65852196650417532ff924c8a2cb0117e2be19.tar.gz focaccia-qemu-8b65852196650417532ff924c8a2cb0117e2be19.zip | |
target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs.
CTR entries are accessed using ctrsource, ctrtarget and ctrdata registers using smcsrind/sscsrind extension. This commits extends the csrind extension to support CTR registers. ctrsource is accessible through xireg CSR, ctrtarget is accessible through xireg1 and ctrdata is accessible through xireg2 CSR. CTR supports maximum depth of 256 entries which are accessed using xiselect range 0x200 to 0x2ff. This commits also adds properties to enable CTR extension. CTR can be enabled using smctr=true and ssctr=true now. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250212-b4-ctr_upstream_v6-v7-1-4e8159ea33bf@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/standard-headers/linux/virtio_pci.h')
0 files changed, 0 insertions, 0 deletions