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authorPeter Maydell <peter.maydell@linaro.org>2017-01-25 16:36:57 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-01-25 16:36:57 +0000
commite32c41e4f65f4d16508fe759a800538a73608839 (patch)
tree288ad9c192a4d6b58d3490eb088450de7153922c /io/task.c
parentae5045ae5b2bbd8ce1335d1b05f9ecacca83a6cf (diff)
parent3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02 (diff)
downloadfocaccia-qemu-e32c41e4f65f4d16508fe759a800538a73608839.tar.gz
focaccia-qemu-e32c41e4f65f4d16508fe759a800538a73608839.zip
Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into staging
target/xtensa updates:

- refactor CCOUNT/CCOMPARE (use QEMU timers instead of instruction counting);
- support icount; run target/xtensa TCG tests with icount;
- implement SMP prerequisites: static vector selection, RUNSTALL and RER/WER.

# gpg: Signature made Wed 25 Jan 2017 00:27:51 GMT
# gpg:                using RSA key 0x51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20170124-xtensa:
  target-xtensa: implement RER/WER instructions
  target/xtensa: tests: clean up interrupt tests
  target/xtensa: tests: add memctl test
  target/xtensa: implement MEMCTL SR
  target/xtensa: fix ICACHE/DCACHE options detection
  target/xtensa: tests: add ccount write tests
  target/xtensa: tests: replace hardcoded interrupt masks
  target/xtensa: tests: fix timer tests
  target/xtensa: tests: run tests with icount
  target/xtensa: don't continue translation after exception
  target/xtensa: support icount
  target/xtensa: refactor CCOUNT/CCOMPARE
  target/xtensa: implement RUNSTALL
  target/xtensa: add static vectors selection

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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