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| author | Daniil Kovalev <dkovalev@compiler-toolchain-for.me> | 2023-04-04 08:21:54 +0300 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2023-05-17 07:20:29 +0200 |
| commit | a0f8d2701b205d9d7986aa555e0566b13dc18fa0 (patch) | |
| tree | ecb6a8bf885d35129a8d3cbb206561b5d57c8894 /linux-user/mips/cpu_loop.c | |
| parent | f443a26cc6c077f792a5114c5229020ecf44ba3b (diff) | |
| download | focaccia-qemu-a0f8d2701b205d9d7986aa555e0566b13dc18fa0.tar.gz focaccia-qemu-a0f8d2701b205d9d7986aa555e0566b13dc18fa0.zip | |
linux-user: Fix mips fp64 executables loading
If a program requires fr1, we should set the FR bit of CP0 control status register and add F64 hardware flag. The corresponding `else if` branch statement is copied from the linux kernel sources (see `arch_check_elf` function in linux/arch/mips/kernel/elf.c). Signed-off-by: Daniil Kovalev <dkovalev@compiler-toolchain-for.me> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230404052153.16617-1-dkovalev@compiler-toolchain-for.me> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'linux-user/mips/cpu_loop.c')
| -rw-r--r-- | linux-user/mips/cpu_loop.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index d5c1c7941d..8735e58bad 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -290,7 +290,10 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) env->CP0_Status |= (1 << CP0St_FR); env->hflags |= MIPS_HFLAG_F64; } - } else if (!prog_req.fre && !prog_req.frdefault && + } else if (prog_req.fr1) { + env->CP0_Status |= (1 << CP0St_FR); + env->hflags |= MIPS_HFLAG_F64; + } else if (!prog_req.fre && !prog_req.frdefault && !prog_req.fr1 && !prog_req.single && !prog_req.soft) { fprintf(stderr, "qemu: Can't find a matching FPU mode\n"); exit(1); |