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| author | Keith Packard <keithp@keithp.com> | 2021-01-08 22:42:52 +0000 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2021-01-18 10:05:06 +0000 |
| commit | a10b9d93ecea0a8f01eb6de56274b1bcb101083b (patch) | |
| tree | 24d8b952a691501fa22791881425539e33535d5a /linux-user/qemu.h | |
| parent | 095f8c029319b79cce487e3b566cd826b93da3e6 (diff) | |
| download | focaccia-qemu-a10b9d93ecea0a8f01eb6de56274b1bcb101083b.tar.gz focaccia-qemu-a10b9d93ecea0a8f01eb6de56274b1bcb101083b.zip | |
riscv: Add semihosting support
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
Diffstat (limited to 'linux-user/qemu.h')
| -rw-r--r-- | linux-user/qemu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 534753ca12..17aa992165 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -109,6 +109,8 @@ typedef struct TaskState { /* FPA state */ FPA11 fpa; # endif +#endif +#if defined(TARGET_ARM) || defined(TARGET_RISCV) int swi_errno; #endif #if defined(TARGET_I386) && !defined(TARGET_X86_64) @@ -122,7 +124,7 @@ typedef struct TaskState { #ifdef TARGET_M68K abi_ulong tp_value; #endif -#if defined(TARGET_ARM) || defined(TARGET_M68K) +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_RISCV) /* Extra fields for semihosted binaries. */ abi_ulong heap_base; abi_ulong heap_limit; |