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| author | Kito Cheng <kito.cheng@sifive.com> | 2021-01-08 22:42:53 +0000 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2021-01-18 10:05:06 +0000 |
| commit | 6b80cb25b4165ae2afa525d084366221a2e9b58d (patch) | |
| tree | a47658827d26826f03bf547ff9bb7d9d514df35b /linux-user/riscv/cpu_loop.c | |
| parent | a10b9d93ecea0a8f01eb6de56274b1bcb101083b (diff) | |
| download | focaccia-qemu-6b80cb25b4165ae2afa525d084366221a2e9b58d.tar.gz focaccia-qemu-6b80cb25b4165ae2afa525d084366221a2e9b58d.zip | |
riscv: Add semihosting support for user mode
This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Keith Packard <keithp@keithp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210107170717.2098982-7-keithp@keithp.com> Message-Id: <20210108224256.2321-18-alex.bennee@linaro.org>
Diffstat (limited to 'linux-user/riscv/cpu_loop.c')
| -rw-r--r-- | linux-user/riscv/cpu_loop.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index aa9e437875..9665dabb09 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -23,6 +23,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "elf.h" +#include "hw/semihosting/common-semi.h" void cpu_loop(CPURISCVState *env) { @@ -91,6 +92,10 @@ void cpu_loop(CPURISCVState *env) sigcode = TARGET_SEGV_MAPERR; sigaddr = env->badaddr; break; + case RISCV_EXCP_SEMIHOST: + env->gpr[xA0] = do_common_semihosting(cs); + env->pc += 4; + break; case EXCP_DEBUG: gdbstep: signum = TARGET_SIGTRAP; |