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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-10-24 15:21:42 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-10-24 15:21:42 +0100 |
| commit | 6b3756503b00d42f1f506815b44ce83aa23ee322 (patch) | |
| tree | 6fedc6f264093e3b68be67c3df291ba69e3f264c /linux-user/strace.c | |
| parent | e67b7aef7c7f67ecd0282e903e0daff806d5d680 (diff) | |
| parent | 310df7a9fe400f32cde8a7edf80daad12cd9cf02 (diff) | |
| download | focaccia-qemu-6b3756503b00d42f1f506815b44ce83aa23ee322.tar.gz focaccia-qemu-6b3756503b00d42f1f506815b44ce83aa23ee322.zip | |
Merge tag 'pull-tcg-20241022' of https://gitlab.com/rth7680/qemu into staging
tcg: Reset data_gen_ptr correctly
tcg/riscv: Implement host vector support
tcg/ppc: Fix tcg_out_rlw_rc
target/i386: Walk NPT in guest real mode
target/i386: Use probe_access_full_mmu in ptw_translate
linux-user: Fix build failure caused by missing __u64 on musl
linux-user: Emulate /proc/self/maps under mmap_lock
linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN
linux-user/ppc: Fix sigmask endianness issue in sigreturn
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* tag 'pull-tcg-20241022' of https://gitlab.com/rth7680/qemu: (24 commits)
linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN
linux-user: Fix build failure caused by missing __u64 on musl
linux-user: Trace rt_sigprocmask's sigsets
linux-user/ppc: Fix sigmask endianness issue in sigreturn
linux-user: Emulate /proc/self/maps under mmap_lock
target/i386: Remove ra parameter from ptw_translate
target/i386: Use probe_access_full_mmu in ptw_translate
target/i386: Walk NPT in guest real mode
include/exec: Improve probe_access_full{, _mmu} documentation
tcg/ppc: Fix tcg_out_rlw_rc
tcg/riscv: Enable native vector support for TCG host
tcg/riscv: Implement vector roti/v/x ops
tcg/riscv: Implement vector shi/s/v ops
tcg/riscv: Implement vector min/max ops
tcg/riscv: Implement vector sat/mul ops
tcg/riscv: Accept constant first argument to sub_vec
tcg/riscv: Implement vector neg ops
tcg/riscv: Implement vector cmp/cmpsel ops
tcg/riscv: Add support for basic vector opcodes
tcg/riscv: Implement vector mov/dup{m/i}
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user/strace.c')
| -rw-r--r-- | linux-user/strace.c | 84 |
1 files changed, 74 insertions, 10 deletions
diff --git a/linux-user/strace.c b/linux-user/strace.c index c3eb3a2706..b70eadc19e 100644 --- a/linux-user/strace.c +++ b/linux-user/strace.c @@ -161,19 +161,20 @@ static const char * const target_signal_name[] = { }; static void -print_signal(abi_ulong arg, int last) +print_signal_1(abi_ulong arg) { - const char *signal_name = NULL; - if (arg < ARRAY_SIZE(target_signal_name)) { - signal_name = target_signal_name[arg]; + qemu_log("%s", target_signal_name[arg]); + } else { + qemu_log(TARGET_ABI_FMT_lu, arg); } +} - if (signal_name == NULL) { - print_raw_param("%ld", arg, last); - return; - } - qemu_log("%s%s", signal_name, get_comma(last)); +static void +print_signal(abi_ulong arg, int last) +{ + print_signal_1(arg); + qemu_log("%s", get_comma(last)); } static void print_si_code(int arg) @@ -718,6 +719,51 @@ print_ipc(CPUArchState *cpu_env, const struct syscallname *name, } #endif +#ifdef TARGET_NR_rt_sigprocmask +static void print_target_sigset_t_1(target_sigset_t *set, int last) +{ + bool first = true; + int i, sig = 1; + + qemu_log("["); + for (i = 0; i < TARGET_NSIG_WORDS; i++) { + abi_ulong bits = 0; + int j; + + __get_user(bits, &set->sig[i]); + for (j = 0; j < sizeof(bits) * 8; j++) { + if (bits & ((abi_ulong)1 << j)) { + if (first) { + first = false; + } else { + qemu_log(" "); + } + print_signal_1(sig); + } + sig++; + } + } + qemu_log("]%s", get_comma(last)); +} + +static void print_target_sigset_t(abi_ulong addr, abi_ulong size, int last) +{ + if (addr && size == sizeof(target_sigset_t)) { + target_sigset_t *set; + + set = lock_user(VERIFY_READ, addr, sizeof(target_sigset_t), 1); + if (set) { + print_target_sigset_t_1(set, last); + unlock_user(set, addr, 0); + } else { + print_pointer(addr, last); + } + } else { + print_pointer(addr, last); + } +} +#endif + /* * Variants for the return value output function */ @@ -3312,11 +3358,29 @@ print_rt_sigprocmask(CPUArchState *cpu_env, const struct syscallname *name, case TARGET_SIG_SETMASK: how = "SIG_SETMASK"; break; } qemu_log("%s,", how); - print_pointer(arg1, 0); + print_target_sigset_t(arg1, arg3, 0); print_pointer(arg2, 0); print_raw_param("%u", arg3, 1); print_syscall_epilogue(name); } + +static void +print_rt_sigprocmask_ret(CPUArchState *cpu_env, const struct syscallname *name, + abi_long ret, abi_long arg0, abi_long arg1, + abi_long arg2, abi_long arg3, abi_long arg4, + abi_long arg5) +{ + if (!print_syscall_err(ret)) { + qemu_log(TARGET_ABI_FMT_ld, ret); + if (arg2) { + qemu_log(" (oldset="); + print_target_sigset_t(arg2, arg3, 1); + qemu_log(")"); + } + } + + qemu_log("\n"); +} #endif #ifdef TARGET_NR_rt_sigqueueinfo |