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authorNicholas Miehlbradt <nicholas@linux.ibm.com>2022-12-20 04:23:29 +0000
committerDaniel Henrique Barboza <danielhb413@gmail.com>2022-12-21 14:17:55 -0300
commit395b5d5b455ac3f6ebf9534454b7187a1d6118a4 (patch)
tree7a4413290f12bb03683a3ba04bb500420fcddb57 /python
parent320c5ad8fffe8ce7562fcc34975398bb4bb50666 (diff)
downloadfocaccia-qemu-395b5d5b455ac3f6ebf9534454b7187a1d6118a4.tar.gz
focaccia-qemu-395b5d5b455ac3f6ebf9534454b7187a1d6118a4.zip
target/ppc: Implement the DEXCR and HDEXCR
Define the DEXCR and HDEXCR as special purpose registers.

Each register occupies two SPR indicies, one which can be read in an
unprivileged state and one which can be modified in the appropriate
priviliged state, however both indicies refer to the same underlying
value.

Note that the ISA uses the abbreviation UDEXCR in two different
contexts: the userspace DEXCR, the SPR index which can be read from
userspace (implemented in this patch), and the ultravisor DEXCR, the
equivalent register for the ultravisor state (not implemented).

Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221220042330.2387944-2-nicholas@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'python')
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