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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2022-04-08 15:13:03 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-04-20 18:00:30 -0300 |
| commit | b34ce592fd3133509793e38adf73c27841aba756 (patch) | |
| tree | 93f526e787bec83bb28a62b9a0016c43d494fd87 /python | |
| parent | 2e8656710a3ac6e79d54b18df9f74b30753448cd (diff) | |
| download | focaccia-qemu-b34ce592fd3133509793e38adf73c27841aba756.tar.gz focaccia-qemu-b34ce592fd3133509793e38adf73c27841aba756.zip | |
ppc/pnv: Remove LSI on the PCIE host bridge
The phb3/phb4/phb5 root ports inherit from the default PCIE root port implementation, which requests a LSI interrupt (#INTA). On real hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch corrects it so that it matches the hardware. As a consequence, the device tree previously generated was bogus, as the root bridge LSI was not properly mapped. On some implementation (powernv9), it was leading to inconsistent interrupt controller (xive) data. With this patch, it is now clean. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220408131303.147840-3-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'python')
0 files changed, 0 insertions, 0 deletions