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| author | Paolo Bonzini <pbonzini@redhat.com> | 2024-12-04 17:14:00 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-12-19 19:36:38 +0100 |
| commit | e1f9353334859ea325f25bd88e01645af63b133b (patch) | |
| tree | 87dc2da72b53ca8f961cfcebcd0b39fad3a3d79a /rust/hw/char/pl011/src/lib.rs | |
| parent | f65314bdd0c287097f7dd4b002c67ceee9729039 (diff) | |
| download | focaccia-qemu-e1f9353334859ea325f25bd88e01645af63b133b.tar.gz focaccia-qemu-e1f9353334859ea325f25bd88e01645af63b133b.zip | |
rust: pl011: fix break errors and definition of Data struct
The Data struct is wrong, and does not show how bits 8-15 of DR
are the receive status. Fix it, and use it to fix break
errors ("c >> 8" in the C code does not translate to
"c.to_be_bytes()[3]").
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to '')
| -rw-r--r-- | rust/hw/char/pl011/src/lib.rs | 41 |
1 files changed, 29 insertions, 12 deletions
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index e3eacb0e6b..463ae60543 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -139,6 +139,21 @@ pub mod registers { //! unused thus treated as zero when read or written. use bilge::prelude::*; + /// Receive Status Register / Data Register common error bits + /// + /// The `UARTRSR` register is updated only when a read occurs + /// from the `UARTDR` register with the same status information + /// that can also be obtained by reading the `UARTDR` register + #[bitsize(8)] + #[derive(Clone, Copy, Default, DebugBits, FromBits)] + pub struct Errors { + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + _reserved_unpredictable: u4, + } + // TODO: FIFO Mode has different semantics /// Data Register, `UARTDR` /// @@ -181,16 +196,18 @@ pub mod registers { /// /// # Source /// ARM DDI 0183G 3.3.1 Data Register, UARTDR - #[bitsize(16)] - #[derive(Clone, Copy, DebugBits, FromBits)] + #[bitsize(32)] + #[derive(Clone, Copy, Default, DebugBits, FromBits)] #[doc(alias = "UARTDR")] pub struct Data { - _reserved: u4, pub data: u8, - pub framing_error: bool, - pub parity_error: bool, - pub break_error: bool, - pub overrun_error: bool, + pub errors: Errors, + _reserved: u16, + } + + impl Data { + // bilge is not very const-friendly, unfortunately + pub const BREAK: Self = Self { value: 1 << 10 }; } // TODO: FIFO Mode has different semantics @@ -220,14 +237,14 @@ pub mod registers { #[bitsize(8)] #[derive(Clone, Copy, DebugBits, FromBits)] pub struct ReceiveStatusErrorClear { - pub framing_error: bool, - pub parity_error: bool, - pub break_error: bool, - pub overrun_error: bool, - _reserved_unpredictable: u4, + pub errors: Errors, } impl ReceiveStatusErrorClear { + pub fn set_from_data(&mut self, data: Data) { + self.set_errors(data.errors()); + } + pub fn reset(&mut self) { // All the bits are cleared to 0 on reset. *self = Self::default(); |