summary refs log tree commit diff stats
path: root/scripts/qapi-commands.py
diff options
context:
space:
mode:
authorCédric Le Goater <clg@kaod.org>2017-02-27 15:29:10 +0100
committerDavid Gibson <david@gibson.dropbear.id.au>2017-03-01 11:23:39 +1100
commit4e4169f7a22a47f1b03457390e105abcf8ebfcc2 (patch)
treeab5ee3a5e2d766afc5911fac05e73b3938cc2c8e /scripts/qapi-commands.py
parent738d5db8240a226ed370b84bf5f5775437bf1158 (diff)
downloadfocaccia-qemu-4e4169f7a22a47f1b03457390e105abcf8ebfcc2.tar.gz
focaccia-qemu-4e4169f7a22a47f1b03457390e105abcf8ebfcc2.zip
ppc/xics: remove set_nr_irqs() handler from XICSStateClass
Today, the ICS (Interrupt Controller Source) object is created and
realized by the init and realize routines of the XICS object, but some
of the parameters are only known at the machine level.

These parameters are passed from the sPAPR machine to the ICS object
in a rather convoluted way using property handlers and a class handler
of the XICS object. The number of irqs required to allocate the IRQ
state objects in the ICS realize routine is one of them.

Let's simplify the process by creating the ICS object along with the
XICS object at the machine level and link the ICS into the XICS list
of ICSs at this level also. In the sPAPR machine, there is only a
single ICS but that will change with the PowerNV machine.

Also, QOMify the creation of the objects and get rid of the
superfluous code.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'scripts/qapi-commands.py')
0 files changed, 0 insertions, 0 deletions