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| author | Anup Patel <anup.patel@wdc.com> | 2020-04-27 13:36:44 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-04-29 13:16:38 -0700 |
| commit | 31e6d70485b1a719ca27e9a2d21f2a61ac497cdf (patch) | |
| tree | 52324705866dabc855d041a1b7ae068ee3a9b14d /scripts/qapi/visit.py | |
| parent | 5b8a986350a9ee2d9d95a76c29017c3c603bb350 (diff) | |
| download | focaccia-qemu-31e6d70485b1a719ca27e9a2d21f2a61ac497cdf.tar.gz focaccia-qemu-31e6d70485b1a719ca27e9a2d21f2a61ac497cdf.zip | |
hw/riscv/spike: Allow more than one CPUs
Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200427080644.168461-4-anup.patel@wdc.com Message-Id: <20200427080644.168461-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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