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authorMichael S. Tsirkin <mst@redhat.com>2011-06-14 17:51:11 +0300
committerMichael S. Tsirkin <mst@redhat.com>2011-06-15 18:27:15 +0300
commitbefeac45d4d9afb587eca9a27d975db4a7950960 (patch)
treeaab24c856a3ea944e287d7f2591bb4bab6a56eb4 /target-alpha/exec.h
parent35f754620615138aaae0ef72602f84c88fd8de0f (diff)
parent0b862cedf36d927818c50584ddd611b0370673df (diff)
downloadfocaccia-qemu-befeac45d4d9afb587eca9a27d975db4a7950960.tar.gz
focaccia-qemu-befeac45d4d9afb587eca9a27d975db4a7950960.zip
Merge remote-tracking branch 'origin/master' into pci
Conflicts:
	hw/virtio-pci.c
Diffstat (limited to 'target-alpha/exec.h')
-rw-r--r--target-alpha/exec.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/target-alpha/exec.h b/target-alpha/exec.h
index 6ae96d148b..7a325e7a75 100644
--- a/target-alpha/exec.h
+++ b/target-alpha/exec.h
@@ -39,7 +39,17 @@ register struct CPUAlphaState *env asm(AREG0);
 
 static inline int cpu_has_work(CPUState *env)
 {
-    return (env->interrupt_request & CPU_INTERRUPT_HARD);
+    /* Here we are checking to see if the CPU should wake up from HALT.
+       We will have gotten into this state only for WTINT from PALmode.  */
+    /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
+       asleep even if (some) interrupts have been asserted.  For now, 
+       assume that if a CPU really wants to stay asleep, it will mask
+       interrupts at the chipset level, which will prevent these bits
+       from being set in the first place.  */
+    return env->interrupt_request & (CPU_INTERRUPT_HARD
+                                     | CPU_INTERRUPT_TIMER
+                                     | CPU_INTERRUPT_SMP
+                                     | CPU_INTERRUPT_MCHK);
 }
 
 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)