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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-09-16 16:54:50 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-09-16 16:54:50 +0100 |
| commit | e3571ae30cd26d19efd4554c25e32ef64d6a36b3 (patch) | |
| tree | b753d7c12df7c6c955bc93e3947c97cd7428125b /target-mips/op_helper.c | |
| parent | ebc231d7daf1f41b23d8b6a6d1234800b86e5fe2 (diff) | |
| parent | 34f939218ce78163171addd63750e1e0300376ab (diff) | |
| download | focaccia-qemu-e3571ae30cd26d19efd4554c25e32ef64d6a36b3.tar.gz focaccia-qemu-e3571ae30cd26d19efd4554c25e32ef64d6a36b3.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20160916' into staging
tcg queued patches # gpg: Signature made Fri 16 Sep 2016 16:14:20 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20160916: tcg: Optimize fence instructions target-i386: Generate fences for x86 target-aarch64: Generate fences for aarch64 target-arm: Generate fences in ARMv7 frontend target-alpha: Generate fence op tcg/tci: Add support for fence tcg/sparc: Add support for fence tcg/s390: Add support for fence tcg/ppc: Add support for fence tcg/mips: Add support for fence tcg/ia64: Add support for fence tcg/arm: Add support for fence tcg/aarch64: Add support for fence tcg/i386: Add support for fence Introduce TCGOpcode for memory barrier cpu-exec: Check -dfilter for -d cpu tcg: Merge GETPC and GETRA tcg: Support arbitrary size + alignment Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/op_helper.c')
| -rw-r--r-- | target-mips/op_helper.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index ea2f2abe19..7af4c2f084 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -4122,10 +4122,10 @@ void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ } #if !defined(CONFIG_USER_ONLY) -MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETRA()) -MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETRA()) -MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETRA()) -MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETRA()) +MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC()) +MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC()) +MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC()) +MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC()) #else MSA_LD_DF(DF_BYTE, b, cpu_ldub_data) MSA_LD_DF(DF_HALF, h, cpu_lduw_data) @@ -4161,17 +4161,17 @@ void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ int mmu_idx = cpu_mmu_index(env, false); \ int i; \ MEMOP_IDX(DF) \ - ensure_writable_pages(env, addr, mmu_idx, GETRA()); \ + ensure_writable_pages(env, addr, mmu_idx, GETPC()); \ for (i = 0; i < DF_ELEMENTS(DF); i++) { \ ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \ } \ } #if !defined(CONFIG_USER_ONLY) -MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETRA()) -MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETRA()) -MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETRA()) -MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA()) +MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC()) +MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC()) +MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC()) +MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC()) #else MSA_ST_DF(DF_BYTE, b, cpu_stb_data) MSA_ST_DF(DF_HALF, h, cpu_stw_data) |