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authorPeter Maydell <peter.maydell@linaro.org>2014-06-16 18:26:21 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-06-16 18:26:21 +0100
commitaf44da87e926ff64260b95f4350d338c4fc113ca (patch)
tree303a18d80e73641bb6e23218ac7b7df0666bcc6b /target-ppc/gdbstub.c
parentf27701510cdce9f76cdad0aaf9fb0bbcb23d299a (diff)
parent9dbae97723e964692364fb43012c6fa5448a661f (diff)
downloadfocaccia-qemu-af44da87e926ff64260b95f4350d338c4fc113ca.tar.gz
focaccia-qemu-af44da87e926ff64260b95f4350d338c4fc113ca.zip
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging
Patch queue for ppc - 2014-06-16

This pull request brings a lot of fun things. Among others we have

  - e500: u-boot firmware support
  - sPAPR: magic page enablement
  - sPAPR: add "compat" CPU option to support older guests
  - sPAPR: refactorings in preparation for VFIO
  - POWER8 live migration
  - mac99: expose bus frequency
  - little endian core dump, gdb and disas support
  - new ppc64le-linux-user target
  - DFP emulation
  - bug fixes

# gpg: Signature made Mon 16 Jun 2014 12:28:32 BST using RSA key ID 03FEDC60
# gpg: Can't check signature: public key not found

* remotes/agraf/tags/signed-ppc-for-upstream: (156 commits)
  spapr_pci: Advertise MSI quota
  PPC: KVM: Make pv hcall endian agnostic
  powerpc: use float64 for frsqrte
  spapr: Add kvm-type property
  spapr: Create SPAPRMachine struct
  linux-user: Tell guest about big host page sizes
  spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
  spapr_hcall: Split h_set_mode()
  target-ppc: Enable DABRX SPR and limit it to <=POWER7
  target-ppc: Enable PPR and VRSAVE SPRs migration
  target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs
  KVM: target-ppc: Enable TM state migration
  target-ppc: Add POWER8's TM SPRs
  target-ppc: Add POWER8's MMCR2/MMCRS SPRs
  target-ppc: Enable FSCR facility check for TAR
  target-ppc: Add POWER8's FSCR SPR
  target-ppc: Add POWER8's TIR SPR
  target-ppc: Refactor class init for POWER7/8
  target-ppc: Switch POWER7/8 classes to use correct PMU SPRs
  target-ppc: Make use of gen_spr_power5p_lpar() for POWER7/8
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-ppc/gdbstub.c')
-rw-r--r--target-ppc/gdbstub.c124
1 files changed, 90 insertions, 34 deletions
diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c
index 1c910902ea..381a3c7e31 100644
--- a/target-ppc/gdbstub.c
+++ b/target-ppc/gdbstub.c
@@ -21,6 +21,55 @@
 #include "qemu-common.h"
 #include "exec/gdbstub.h"
 
+static int ppc_gdb_register_len(int n)
+{
+    switch (n) {
+    case 0 ... 31:
+        /* gprs */
+        return sizeof(target_ulong);
+    case 32 ... 63:
+        /* fprs */
+        if (gdb_has_xml) {
+            return 0;
+        }
+        return 8;
+    case 66:
+        /* cr */
+        return 4;
+    case 64:
+        /* nip */
+    case 65:
+        /* msr */
+    case 67:
+        /* lr */
+    case 68:
+        /* ctr */
+    case 69:
+        /* xer */
+        return sizeof(target_ulong);
+    case 70:
+        /* fpscr */
+        if (gdb_has_xml) {
+            return 0;
+        }
+        return sizeof(target_ulong);
+    default:
+        return 0;
+    }
+}
+
+
+static void ppc_gdb_swap_register(uint8_t *mem_buf, int n, int len)
+{
+    if (len == 4) {
+        bswap32s((uint32_t *)mem_buf);
+    } else if (len == 8) {
+        bswap64s((uint64_t *)mem_buf);
+    } else {
+        g_assert_not_reached();
+    }
+}
+
 /* Old gdb always expects FP registers.  Newer (xml-aware) gdb only
  * expects whatever the target description contains.  Due to a
  * historical mishap the FP registers appear in between core integer
@@ -32,23 +81,26 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
 {
     PowerPCCPU *cpu = POWERPC_CPU(cs);
     CPUPPCState *env = &cpu->env;
+    int r = ppc_gdb_register_len(n);
+
+    if (!r) {
+        return r;
+    }
 
     if (n < 32) {
         /* gprs */
-        return gdb_get_regl(mem_buf, env->gpr[n]);
+        gdb_get_regl(mem_buf, env->gpr[n]);
     } else if (n < 64) {
         /* fprs */
-        if (gdb_has_xml) {
-            return 0;
-        }
         stfq_p(mem_buf, env->fpr[n-32]);
-        return 8;
     } else {
         switch (n) {
         case 64:
-            return gdb_get_regl(mem_buf, env->nip);
+            gdb_get_regl(mem_buf, env->nip);
+            break;
         case 65:
-            return gdb_get_regl(mem_buf, env->msr);
+            gdb_get_regl(mem_buf, env->msr);
+            break;
         case 66:
             {
                 uint32_t cr = 0;
@@ -56,50 +108,57 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
                 for (i = 0; i < 8; i++) {
                     cr |= env->crf[i] << (32 - ((i + 1) * 4));
                 }
-                return gdb_get_reg32(mem_buf, cr);
+                gdb_get_reg32(mem_buf, cr);
+                break;
             }
         case 67:
-            return gdb_get_regl(mem_buf, env->lr);
+            gdb_get_regl(mem_buf, env->lr);
+            break;
         case 68:
-            return gdb_get_regl(mem_buf, env->ctr);
+            gdb_get_regl(mem_buf, env->ctr);
+            break;
         case 69:
-            return gdb_get_regl(mem_buf, env->xer);
+            gdb_get_regl(mem_buf, env->xer);
+            break;
         case 70:
-            {
-                if (gdb_has_xml) {
-                    return 0;
-                }
-                return gdb_get_reg32(mem_buf, env->fpscr);
-            }
+            gdb_get_reg32(mem_buf, env->fpscr);
+            break;
         }
     }
-    return 0;
+    if (msr_le) {
+        /* If cpu is in LE mode, convert memory contents to LE. */
+        ppc_gdb_swap_register(mem_buf, n, r);
+    }
+    return r;
 }
 
 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 {
     PowerPCCPU *cpu = POWERPC_CPU(cs);
     CPUPPCState *env = &cpu->env;
+    int r = ppc_gdb_register_len(n);
 
+    if (!r) {
+        return r;
+    }
+    if (msr_le) {
+        /* If cpu is in LE mode, convert memory contents to LE. */
+        ppc_gdb_swap_register(mem_buf, n, r);
+    }
     if (n < 32) {
         /* gprs */
         env->gpr[n] = ldtul_p(mem_buf);
-        return sizeof(target_ulong);
     } else if (n < 64) {
         /* fprs */
-        if (gdb_has_xml) {
-            return 0;
-        }
         env->fpr[n-32] = ldfq_p(mem_buf);
-        return 8;
     } else {
         switch (n) {
         case 64:
             env->nip = ldtul_p(mem_buf);
-            return sizeof(target_ulong);
+            break;
         case 65:
             ppc_store_msr(env, ldtul_p(mem_buf));
-            return sizeof(target_ulong);
+            break;
         case 66:
             {
                 uint32_t cr = ldl_p(mem_buf);
@@ -107,25 +166,22 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
                 for (i = 0; i < 8; i++) {
                     env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
                 }
-                return 4;
+                break;
             }
         case 67:
             env->lr = ldtul_p(mem_buf);
-            return sizeof(target_ulong);
+            break;
         case 68:
             env->ctr = ldtul_p(mem_buf);
-            return sizeof(target_ulong);
+            break;
         case 69:
             env->xer = ldtul_p(mem_buf);
-            return sizeof(target_ulong);
+            break;
         case 70:
             /* fpscr */
-            if (gdb_has_xml) {
-                return 0;
-            }
             store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
-            return sizeof(target_ulong);
+            break;
         }
     }
-    return 0;
+    return r;
 }