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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-02-09 16:49:50 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-02-09 16:49:50 +0000 |
| commit | 40569b7edc2959c7460211de0b30bbdbb87626e4 (patch) | |
| tree | c19948daf6614dda235e1c4b7fc21ada42859432 /target-ppc/translate_init.c | |
| parent | 071fc3b1cda1ad6f8d4b83cdf3f8cf8c395f9404 (diff) | |
| download | focaccia-qemu-40569b7edc2959c7460211de0b30bbdbb87626e4.tar.gz focaccia-qemu-40569b7edc2959c7460211de0b30bbdbb87626e4.zip | |
target-ppc: Model SPE floating-point instructions more accurately
Single-precision and double-precision floating-point instructions should be separated into their own categories, since some chips only support single-precision instructions. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6575 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to '')
| -rw-r--r-- | target-ppc/translate_init.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index c808923980..8d147c81d7 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -3984,7 +3984,7 @@ static void init_proc_G2LE (CPUPPCState *env) * all SPE multiply-accumulate instructions */ #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \ - PPC_SPE | PPC_SPEFPU | \ + PPC_SPE | PPC_SPE_SINGLE | \ PPC_WRTEE | PPC_RFDI | \ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ @@ -4147,13 +4147,13 @@ static void init_proc_e300 (CPUPPCState *env) ppc6xx_irq_init(env); } -/* e500 core */ -#define POWERPC_INSNS_e500 (PPC_INSNS_BASE | PPC_ISEL | \ - PPC_SPE | PPC_SPEFPU | \ - PPC_WRTEE | PPC_RFDI | \ - PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ - PPC_MEM_TLBSYNC | PPC_TLBIVAX | \ +/* e500 core */ +#define POWERPC_INSNS_e500 (PPC_INSNS_BASE | PPC_ISEL | \ + PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \ + PPC_WRTEE | PPC_RFDI | \ + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ + PPC_MEM_TLBSYNC | PPC_TLBIVAX | \ PPC_BOOKE) #define POWERPC_MSRM_e500 (0x000000000606FF30ULL) #define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL) @@ -9431,7 +9431,7 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg, 34, "power-altivec.xml", 0); } - if ((def->insns_flags & PPC_SPE) | (def->insns_flags & PPC_SPEFPU)) { + if (def->insns_flags & PPC_SPE) { gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg, 34, "power-spe.xml", 0); } |