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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-08-15 22:26:52 +1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-08-30 16:38:46 +0100 |
| commit | 99e441107efb34a8af990cedbfbda0567d0bb387 (patch) | |
| tree | 12ebae71b571a4932d66a56c76347cfcae154733 /target/arm/cpu-features.h | |
| parent | 905c2c34fe3432879f31ef0aa64ce478e573276b (diff) | |
| download | focaccia-qemu-99e441107efb34a8af990cedbfbda0567d0bb387.tar.gz focaccia-qemu-99e441107efb34a8af990cedbfbda0567d0bb387.zip | |
target/arm: Implement FEAT_LSE128
This feature contains the LDCLRP, LDSETP, and SWPP instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250815122653.701782-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu-features.h')
| -rw-r--r-- | target/arm/cpu-features.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 451b37b5b3..e49e0ae3af 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -411,6 +411,11 @@ static inline bool isar_feature_aa64_lse(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >= 2; } +static inline bool isar_feature_aa64_lse128(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >= 3; +} + static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) != 0; |