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| author | Gustavo Romero <gustavo.romero@linaro.org> | 2025-08-26 11:21:28 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-08-30 16:37:22 +0100 |
| commit | 6e6d5fb4b928f09b46d0fa99830d75cddb22f73b (patch) | |
| tree | 71c13a42cb6327048ac34891ca5652ff99209717 /target/arm/cpu.c | |
| parent | 8a60ffe9a8f46ed514656eb4a40d1386c439daf8 (diff) | |
| download | focaccia-qemu-6e6d5fb4b928f09b46d0fa99830d75cddb22f73b.tar.gz focaccia-qemu-6e6d5fb4b928f09b46d0fa99830d75cddb22f73b.zip | |
target/arm: Implement FEAT_TCR2 and enable with -cpu max
Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers. These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250727074202.83141-5-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-5-gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.c')
| -rw-r--r-- | target/arm/cpu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2ab04cb5f7..27a4610da5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -644,6 +644,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int target_el) if (cpu_isar_feature(aa64_fgt, cpu)) { env->cp15.scr_el3 |= SCR_FGTEN; } + if (cpu_isar_feature(aa64_tcr2, cpu)) { + env->cp15.scr_el3 |= SCR_TCR2EN; + } if (cpu_isar_feature(aa64_sctlr2, cpu)) { env->cp15.scr_el3 |= SCR_SCTLR2EN; } |