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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-04-18 16:20:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-30 15:01:07 +0100 |
| commit | f7ddd7b6a1f90cae677303e96b91e866a1570f6a (patch) | |
| tree | 305a47052871f43ba3d8cc19cd4fd60699a78fc9 /target/arm/helper.c | |
| parent | 74360f3544be380f3a6f7a0f1cd8082ddd4a75ad (diff) | |
| download | focaccia-qemu-f7ddd7b6a1f90cae677303e96b91e866a1570f6a.tar.gz focaccia-qemu-f7ddd7b6a1f90cae677303e96b91e866a1570f6a.zip | |
target/arm: Implement ID_AA64MMFR3_EL1
Newer versions of the Arm ARM (e.g. rev K.a) now define fields for ID_AA64MMFR3_EL1. Implement this register, so that we can set the fields if we need to. There's no behaviour change here since we don't currently set the register value to non-zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 6b224826fb..bb0e1baf62 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9004,11 +9004,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64mmfr2 }, - { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr3 }, { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, @@ -9165,6 +9165,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .exported_bits = R_ID_AA64MMFR1_AFP_MASK }, { .name = "ID_AA64MMFR2_EL1", .exported_bits = R_ID_AA64MMFR2_AT_MASK }, + { .name = "ID_AA64MMFR3_EL1", + .exported_bits = 0 }, { .name = "ID_AA64MMFR*_EL1_RESERVED", .is_glob = true }, { .name = "ID_AA64DFR0_EL1", |