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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-10-12 17:06:50 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-10-12 17:06:50 +0100 |
| commit | f90ea7ba7c5ae7010ee0ce062207ae42530f57d6 (patch) | |
| tree | 74f97fd1d01bc8f8b372387bd98d08a7ad12c7df /target/arm/internals.h | |
| parent | a0b261db8c030813e30a39eae47359ac2a37f7e2 (diff) | |
| parent | cf5f7937b05c84d5565134f058c00cd48304a117 (diff) | |
| download | focaccia-qemu-f90ea7ba7c5ae7010ee0ce062207ae42530f57d6.tar.gz focaccia-qemu-f90ea7ba7c5ae7010ee0ce062207ae42530f57d6.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171012' into staging
target-arm queue: * v8M: SG, BLXNS, secure-return * v8M: fixes for coverity issues in previous patches * arm: fix armv7m_init() declaration to match definition * watchdog/aspeed: fix variable type to store reload value # gpg: Signature made Thu 12 Oct 2017 17:02:49 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20171012: nvic: Fix miscalculation of offsets into ITNS array nvic: Add missing 'break' target/arm: Implement SG instruction corner cases target/arm: Support some Thumb insns being always unconditional target-arm: Simplify insn_crosses_page() target/arm: Pull Thumb insn word loads up to top level target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1 target/arm: Implement secure function return target/arm: Implement BLXNS target/arm: Implement SG instruction target/arm: Add M profile secure MMU index values to get_a32_user_mem_index() arm: fix armv7m_init() declaration to match definition watchdog/aspeed: fix variable type to store reload value Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
| -rw-r--r-- | target/arm/internals.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h index fd9a7e8181..43106a2d6c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -60,6 +60,7 @@ static inline bool excp_is_internal(int excp) FIELD(V7M_CONTROL, NPRIV, 0, 1) FIELD(V7M_CONTROL, SPSEL, 1, 1) FIELD(V7M_CONTROL, FPCA, 2, 1) +FIELD(V7M_CONTROL, SFPA, 3, 1) /* Bit definitions for v7M exception return payload */ FIELD(V7M_EXCRET, ES, 0, 1) @@ -71,6 +72,13 @@ FIELD(V7M_EXCRET, DCRS, 5, 1) FIELD(V7M_EXCRET, S, 6, 1) FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ +/* Minimum value which is a magic number for exception return */ +#define EXC_RETURN_MIN_MAGIC 0xff000000 +/* Minimum number which is a magic number for function or exception return + * when using v8M security extension + */ +#define FNC_RETURN_MIN_MAGIC 0xfefffffe + /* We use a few fake FSR values for internal purposes in M profile. * M profile cores don't have A/R format FSRs, but currently our * get_phys_addr() code assumes A/R profile and reports failures via |