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| author | Stefan Hajnoczi <stefanha@redhat.com> | 2025-04-23 09:29:33 -0400 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2025-04-23 09:29:33 -0400 |
| commit | 91d0d16b44c93fa82cf76ae12990ce3aa96096c9 (patch) | |
| tree | e1f7e247ba9cfa043527356c6b522f0c2c5b40b9 /target/avr/cpu.h | |
| parent | 55f5bf716a65f67663d0769bcb8c017764b3e53a (diff) | |
| parent | eba24b60a72115e21e850977b3019aaf037c66c9 (diff) | |
| download | focaccia-qemu-91d0d16b44c93fa82cf76ae12990ce3aa96096c9.tar.gz focaccia-qemu-91d0d16b44c93fa82cf76ae12990ce3aa96096c9.zip | |
Merge tag 'pull-avr-20250422' of https://gitlab.com/rth7680/qemu into staging
target/avr: Fix buffer read in avr_print_insn target/avr: Improve decode of LDS, STS target/avr: Move cpu register accesses into system memory target/avr: Increase TARGET_PAGE_BITS to 10 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmgIBb4dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9wcgf/b0pwvg5GlDEtowUU # L21jCyzh0zkYTBQ4SYiGKI1jYx3wuJAEyDx8jQ8iFZA+5Vv43aUQO0ghy301Xmc+ # wrBDhVbd+cSCNPobd8uthoDfBoMO6IIvQ10Rc9S/iCVs7idhrS/vCk25UqWkHHo6 # BYI8mZCTwIo/UnE4B9g5+ccvTqiXIzOYDWxRo31Fb4GJclPlELV0MS/IO377W3Rs # t43BGDbzyJW1irUOzBsCxqZ8QogUwOve5h67tzJK53ETqqZVlRnuH3mvirtlL3R0 # 0AMFYwm0ygr+rkmQ/AfQ2D1QPiVz0oALV0P1KKNaUuv39WAeWEVEcIuDMvwy9XqG # pgI+uw== # =/fBY # -----END PGP SIGNATURE----- # gpg: Signature made Tue 22 Apr 2025 17:10:22 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-avr-20250422' of https://gitlab.com/rth7680/qemu: target/avr: Increase TARGET_PAGE_BITS to 10 hw/avr: Prepare for TARGET_PAGE_SIZE > 256 target/avr: Use do_stb in avr_cpu_do_interrupt target/avr: Use cpu_stb_mmuidx_ra in helper_fullwr target/avr: Remove NUMBER_OF_IO_REGISTERS target/avr: Move cpu register accesses into system memory target/avr: Add defines for i/o port registers target/avr: Remove OFFSET_CPU_REGISTERS target/avr: Improve decode of LDS, STS Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'target/avr/cpu.h')
| -rw-r--r-- | target/avr/cpu.h | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 06f5ae4d1b..9862705c6a 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memory.h" #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" @@ -44,8 +45,16 @@ /* Number of CPU registers */ #define NUMBER_OF_CPU_REGISTERS 32 -/* Number of IO registers accessible by ld/st/in/out */ -#define NUMBER_OF_IO_REGISTERS 64 + +/* CPU registers mapped into i/o ports 0x38-0x3f. */ +#define REG_38_RAMPD 0 +#define REG_38_RAMPX 1 +#define REG_38_RAMPY 2 +#define REG_38_RAMPZ 3 +#define REG_38_EIDN 4 +#define REG_38_SPL 5 +#define REG_38_SPH 6 +#define REG_38_SREG 7 /* * Offsets of AVR memory regions in host memory space. @@ -60,8 +69,6 @@ #define OFFSET_CODE 0x00000000 /* CPU registers, IO registers, and SRAM */ #define OFFSET_DATA 0x00800000 -/* CPU registers specifically, these are mapped at the start of data */ -#define OFFSET_CPU_REGISTERS OFFSET_DATA /* * IO registers, including status register, stack pointer, and memory * mapped peripherals, mapped just after CPU registers @@ -144,6 +151,9 @@ struct ArchCPU { CPUAVRState env; + MemoryRegion cpu_reg1; + MemoryRegion cpu_reg2; + /* Initial value of stack pointer */ uint32_t init_sp; }; @@ -244,6 +254,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +extern const MemoryRegionOps avr_cpu_reg1; +extern const MemoryRegionOps avr_cpu_reg2; + #include "exec/cpu-all.h" #endif /* QEMU_AVR_CPU_H */ |