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authorPeter Maydell <peter.maydell@linaro.org>2019-05-17 10:28:23 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-05-17 10:28:23 +0100
commitb0f9690e78827d55a508c73432c73f057f59fd41 (patch)
treeedd913c2d05dd5d2113705e320c0c6c05ceee142 /target/m68k/op_helper.c
parentd8276573da58e8ce78dab8c46dd660efd664bcb7 (diff)
parent60d3d0cfeb1658d2827d6a4f0df27252bb36baba (diff)
downloadfocaccia-qemu-b0f9690e78827d55a508c73432c73f057f59fd41.tar.gz
focaccia-qemu-b0f9690e78827d55a508c73432c73f057f59fd41.zip
Merge remote-tracking branch 'remotes/vivier/tags/m68k-staging-pull-request' into staging
code cleanup, switch to transaction_failed hook

# gpg: Signature made Thu 16 May 2019 23:33:00 BST
# gpg:                using RSA key F30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier/tags/m68k-staging-pull-request:
  target/m68k: Optimize rotate_x() using extract_i32()
  target/m68k: Fix a tcg_temp leak
  target/m68k: Reduce the l1 TCGLabel scope
  target/m68k: Switch to transaction_failed hook
  target/m68k: In get_physical_address() check for memory access failures
  target/m68k: In dump_address_map() check for memory access failures

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	target/m68k/cpu.h
Diffstat (limited to 'target/m68k/op_helper.c')
-rw-r--r--target/m68k/op_helper.c20
1 files changed, 8 insertions, 12 deletions
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index d421614727..1ecc772b5c 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -439,19 +439,15 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KState *env)
     do_interrupt_all(env, 1);
 }
 
-void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
-                                bool is_exec, int is_asi, unsigned size)
+void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
+                                 unsigned size, MMUAccessType access_type,
+                                 int mmu_idx, MemTxAttrs attrs,
+                                 MemTxResult response, uintptr_t retaddr)
 {
     M68kCPU *cpu = M68K_CPU(cs);
     CPUM68KState *env = &cpu->env;
-#ifdef DEBUG_UNASSIGNED
-    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
-             addr, is_write, is_exec);
-#endif
-    if (env == NULL) {
-        /* when called from gdb, env is NULL */
-        return;
-    }
+
+    cpu_restore_state(cs, retaddr, true);
 
     if (m68k_feature(env, M68K_FEATURE_M68040)) {
         env->mmu.mmusr = 0;
@@ -461,7 +457,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
         if (env->sr & SR_S) { /* SUPERVISOR */
             env->mmu.ssw |= M68K_TM_040_SUPER;
         }
-        if (is_exec) { /* instruction or data */
+        if (access_type == MMU_INST_FETCH) { /* instruction or data */
             env->mmu.ssw |= M68K_TM_040_CODE;
         } else {
             env->mmu.ssw |= M68K_TM_040_DATA;
@@ -479,7 +475,7 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
             break;
         }
 
-        if (!is_write) {
+        if (access_type != MMU_DATA_STORE) {
             env->mmu.ssw |= M68K_RW_040;
         }