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authorPeter Maydell <peter.maydell@linaro.org>2019-09-04 10:16:00 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-09-04 10:16:00 +0100
commit379d83f2c92879f4418aa9c57fd1fcbc3c82d384 (patch)
treeba5f251e156c27703fbc09f1e4f4a8808f58399f /target/mips/op_helper.c
parent03a6190518206175f280704430811919211ce96a (diff)
parentabd4393d769d9fe2333b2e83e00f911a78475943 (diff)
downloadfocaccia-qemu-379d83f2c92879f4418aa9c57fd1fcbc3c82d384.tar.gz
focaccia-qemu-379d83f2c92879f4418aa9c57fd1fcbc3c82d384.zip
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-29-2019' into staging
MIPS queue for August 29th, 2019

# gpg: Signature made Thu 29 Aug 2019 11:19:28 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-aug-29-2019: (31 commits)
  target/mips: Fix emulation of ST.W in system mode
  target/mips: Clean up handling of CP0 register 31
  target/mips: Clean up handling of CP0 register 30
  target/mips: Clean up handling of CP0 register 29
  target/mips: Clean up handling of CP0 register 28
  target/mips: Clean up handling of CP0 register 27
  target/mips: Clean up handling of CP0 register 26
  target/mips: Clean up handling of CP0 register 25
  target/mips: Clean up handling of CP0 register 24
  target/mips: Clean up handling of CP0 register 23
  target/mips: Clean up handling of CP0 register 20
  target/mips: Clean up handling of CP0 register 19
  target/mips: Clean up handling of CP0 register 18
  target/mips: Clean up handling of CP0 register 17
  target/mips: Clean up handling of CP0 register 16
  target/mips: Clean up handling of CP0 register 15
  target/mips: Clean up handling of CP0 register 14
  target/mips: Clean up handling of CP0 register 13
  target/mips: Clean up handling of CP0 register 12
  target/mips: Clean up handling of CP0 register 11
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/mips/op_helper.c')
-rw-r--r--target/mips/op_helper.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index f88a3ab904..5b8bb203f0 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4692,15 +4692,15 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
     ensure_writable_pages(env, addr, mmu_idx, GETPC());
 #if !defined(CONFIG_USER_ONLY)
 #if !defined(HOST_WORDS_BIGENDIAN)
-    helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]);
-    helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]);
-    helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]);
-    helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]);
+    helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
+    helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
+    helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
+    helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
 #else
-    helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]);
-    helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]);
-    helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]);
-    helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]);
+    helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
+    helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
+    helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
+    helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
 #endif
 #else
 #if !defined(HOST_WORDS_BIGENDIAN)