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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-05-06 14:49:25 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:53:33 -0700 |
| commit | 62f2b0389ff6fc7856b801bb5bee1c2d364d3e6c (patch) | |
| tree | 67be040ef1a5bab9ee48aabfcaffdb15432d4409 /target/openrisc/cpu.c | |
| parent | fe636d3722bf266c7b1bd3ca12fa53fb78ceffa0 (diff) | |
| download | focaccia-qemu-62f2b0389ff6fc7856b801bb5bee1c2d364d3e6c.tar.gz focaccia-qemu-62f2b0389ff6fc7856b801bb5bee1c2d364d3e6c.zip | |
target/openrisc: Add support for ORFPX64A32
This is hardware support for double-precision floating-point using pairs of 32-bit registers. Fix latent bugs in the heretofore unused helper_itofd and helper_ftoid. Include the bit for cpu "any". Change the default cpu for linux-user to "any". Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/cpu.c')
| -rw-r--r-- | target/openrisc/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f3c8134531..b931605e62 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -132,7 +132,7 @@ static void openrisc_any_initfn(Object *obj) cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | - CPUCFGR_AVRP | CPUCFGR_EVBARP; + CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; /* 1Way, TLB_SIZE entries. */ cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) |