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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-04-24 22:24:06 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-30 12:45:05 -0700 |
| commit | 0f81774dd1c19de5dedb3c8f2d74e5b9a73d8c12 (patch) | |
| tree | c06b1e05129830505ffa818f422b4a1a56d9a930 /target/openrisc/exception_helper.c | |
| parent | 3ea423c27f4eabee5068fce27412761fa3db8b0f (diff) | |
| download | focaccia-qemu-0f81774dd1c19de5dedb3c8f2d74e5b9a73d8c12.tar.gz focaccia-qemu-0f81774dd1c19de5dedb3c8f2d74e5b9a73d8c12.zip | |
target/riscv: Include missing 'accel/tcg/getpc.h' in csr.c
"accel/tcg/getpc.h" is pulled in indirectly. Include it
explicitly to avoid when refactoring unrelated headers:
target/riscv/csr.c:2117:25: error: call to undeclared function 'GETPC' [-Wimplicit-function-declaration]
2117 | if ((val & RVC) && (GETPC() & ~3) != 0) {
| ^
Note the TODO comment around GETPC() added upon introduction in
commit f18637cd611 ("RISC-V: Add misa runtime write support"):
2099 static RISCVException write_misa(CPURISCVState *env, int csrno,
2100 target_ulong val)
2101 {
...
2113 /*
2114 * Suppress 'C' if next instruction is not aligned
2115 * TODO: this should check next_pc
2116 */
2117 if ((val & RVC) && (GETPC() & ~3) != 0) {
2118 val &= ~RVC;
2119 }
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250424202412.91612-8-philmd@linaro.org>
Diffstat (limited to 'target/openrisc/exception_helper.c')
0 files changed, 0 insertions, 0 deletions