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| author | Paolo Bonzini <pbonzini@redhat.com> | 2025-02-18 11:31:30 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-05-20 08:18:53 +0200 |
| commit | a6ba81424a7e751fbcee40dc1f5826ba29fddd30 (patch) | |
| tree | d1b4d7b7627fd401d56fb63a2ada9a7a633a3883 /target/riscv/cpu.h | |
| parent | 407254031edd649e6acde736e3f7e95bb0fdf299 (diff) | |
| download | focaccia-qemu-a6ba81424a7e751fbcee40dc1f5826ba29fddd30.tar.gz focaccia-qemu-a6ba81424a7e751fbcee40dc1f5826ba29fddd30.zip | |
target/riscv: add more RISCVCPUDef fields
Allow using RISCVCPUDef to replicate all the logic of custom .instance_init functions. To simulate inheritance, merge the child's RISCVCPUDef with the parent and then finally move it to the CPUState at the end of TYPE_RISCV_CPU's own instance_init function. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target/riscv/cpu.h')
| -rw-r--r-- | target/riscv/cpu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d2d4db95c1..29b01e9aa8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -540,6 +540,10 @@ struct ArchCPU { typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + uint32_t misa_ext; + int priv_spec; + int32_t vext_spec; + RISCVCPUConfig cfg; } RISCVCPUDef; /** |