Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging

First RISC-V PR for 8.1

* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse in XVentanaCondOps
* Fix invalid riscv,event-to-mhpmcounters entry
* Support subsets of code size reduction extension
* Fix itrigger when icount is used
* Simplification for RVH related check and code style fix
* Add signature dump function for spike to run ACT tests
* Rework MISA writing
* Fix mstatus.MPP related support
* Use check for relationship between Zdinx/Zhinx{min} and Zfinx
* Fix the H extension TVM trap
* A large collection of mstatus sum changes and cleanups
* Zero init APLIC internal state
* Implement query-cpu-definitions
* Restore the predicate() NULL check behavior
* Fix Guest Physical Address Translation
* Make sure an exception is raised if a pte is malformed
* Add Ventana's Veyron V1 CPU

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* tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu: (89 commits)
  target/riscv: add Ventana's Veyron V1 CPU
  riscv: Make sure an exception is raised if a pte is malformed
  target/riscv: Fix Guest Physical Address Translation
  target/riscv: Restore the predicate() NULL check behavior
  target/riscv: add TYPE_RISCV_DYNAMIC_CPU
  target/riscv: add query-cpy-definitions support
  target/riscv: add CPU QOM header
  hw/intc/riscv_aplic: Zero init APLIC internal state
  target/riscv: Reorg sum check in get_physical_address
  target/riscv: Reorg access check in get_physical_address
  target/riscv: Merge checks for reserved pte flags
  target/riscv: Don't modify SUM with is_debug
  target/riscv: Suppress pte update with is_debug
  target/riscv: Move leaf pte processing out of level loop
  target/riscv: Hoist pbmte and hade out of the level loop
  target/riscv: Hoist second stage mode change to callers
  target/riscv: Check SUM in the correct register
  target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
  target/riscv: Move hstatus.spvp check to check_access_hlsv
  target/riscv: Introduce mmuidx_2stage
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

1 files changed, 5 insertions, 4 deletions

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 840d1ec5c6..524bede865 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -130,7 +130,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
 
 static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
 {
-    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
     if (n < 32) {
         int i;
         int cnt = 0;
@@ -146,7 +146,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
 
 static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
 {
-    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
     if (n < 32) {
         int i;
         for (i = 0; i < vlenb; i += 8) {
@@ -203,7 +203,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
     if (n == 0) {
 #ifndef CONFIG_USER_ONLY
         cs->priv = ldtul_p(mem_buf) & 0x3;
-        if (cs->priv == PRV_H) {
+        if (cs->priv == PRV_RESERVED) {
             cs->priv = PRV_S;
         }
 #endif
@@ -321,7 +321,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
     }
     if (env->misa_ext & RVV) {
         int base_reg = cs->gdb_num_regs;
-        gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
+        gdb_register_coprocessor(cs, riscv_gdb_get_vector,
+                                 riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_xml(cs, base_reg),
                                  "riscv-vector.xml", 0);
     }