diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-14 18:24:19 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-05 11:53:13 -0800 |
| commit | 2a1905c79e1009600e96e7d1d0c592d573e94dbd (patch) | |
| tree | 681d8dc486672ac158a19919b5bef4f62069abad /target/sparc/cpu.h | |
| parent | b1fa27fcc88428f79de772825ab50cfca14bfc5f (diff) | |
| download | focaccia-qemu-2a1905c79e1009600e96e7d1d0c592d573e94dbd.tar.gz focaccia-qemu-2a1905c79e1009600e96e7d1d0c592d573e94dbd.zip | |
target/sparc: Split psr and xcc into components
Step in removing CC_OP: change the representation of CC_OP_FLAGS. The 8 bits are distributed between 6 variables, which should make it easy to keep up to date. The code within cc_helper.c is quite ugly but is only temporary. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/sparc/cpu.h')
| -rw-r--r-- | target/sparc/cpu.h | 30 |
1 files changed, 27 insertions, 3 deletions
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 955329f6c9..ea8a04c6e3 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -149,7 +149,7 @@ enum { */ enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ - CC_OP_FLAGS, /* all cc are back in status register */ + CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ CC_OP_DIV, /* modify N, Z and V, C = 0*/ CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ @@ -458,6 +458,32 @@ struct CPUArchState { target_ulong npc; /* next program counter */ target_ulong y; /* multiply/divide register */ + /* + * Bit 31 is for icc, bit 63 for xcc. + * Other bits are garbage. + */ + target_long cc_N; + target_long cc_V; + + /* + * Z is represented as == 0; any non-zero value is !Z. + * For sparc64, the high 32-bits of icc.Z are garbage. + */ + target_ulong icc_Z; +#ifdef TARGET_SPARC64 + target_ulong xcc_Z; +#endif + + /* + * For sparc32, icc.C is boolean. + * For sparc64, xcc.C is boolean; + * icc.C is bit 32 with other bits garbage. + */ + target_ulong icc_C; +#ifdef TARGET_SPARC64 + target_ulong xcc_C; +#endif + /* emulator internal flags handling */ target_ulong cc_src, cc_src2; target_ulong cc_dst; @@ -466,7 +492,6 @@ struct CPUArchState { target_ulong cond; /* conditional branch result (XXX: save it in a temporary register when possible) */ - uint32_t psr; /* processor state register */ target_ulong fsr; /* FPU state register */ CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ uint32_t cwp; /* index of current register window (extracted @@ -522,7 +547,6 @@ struct CPUArchState { #define MAXTL_MAX 8 #define MAXTL_MASK (MAXTL_MAX - 1) trap_state ts[MAXTL_MAX]; - uint32_t xcc; /* Extended integer condition codes */ uint32_t asi; uint32_t pstate; uint32_t tl; |