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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-14 21:55:27 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-05 12:03:17 -0800 |
| commit | b597eedcce0de84ff573a6be2cd6a89c7fa0fd8e (patch) | |
| tree | 33c3ab8ac42da284da0c13630f0728f3763865dd /target/sparc/cpu.h | |
| parent | 68524e83f8fbe23dca37dc5b847fb558d75c8fab (diff) | |
| download | focaccia-qemu-b597eedcce0de84ff573a6be2cd6a89c7fa0fd8e.tar.gz focaccia-qemu-b597eedcce0de84ff573a6be2cd6a89c7fa0fd8e.zip | |
target/sparc: Remove CC_OP leftovers
All instructions have been converted to generate full condition codes explicitly. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/sparc/cpu.h')
| -rw-r--r-- | target/sparc/cpu.h | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index a7999eaab5..3e361a5b75 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -137,22 +137,6 @@ enum { #define PSR_CWP 0x1f #endif -#define CC_SRC (env->cc_src) -#define CC_SRC2 (env->cc_src2) -#define CC_DST (env->cc_dst) -#define CC_OP (env->cc_op) - -/* Even though lazy evaluation of CPU condition codes tends to be less - * important on RISC systems where condition codes are only updated - * when explicitly requested, SPARC uses it to update 32-bit and 64-bit - * condition codes. - */ -enum { - CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ - CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ - CC_OP_NB, -}; - /* Trap base register */ #define TBR_BASE_MASK 0xfffff000 @@ -474,11 +458,6 @@ struct CPUArchState { target_ulong xcc_C; #endif - /* emulator internal flags handling */ - target_ulong cc_src, cc_src2; - target_ulong cc_dst; - uint32_t cc_op; - target_ulong cond; /* conditional branch result (XXX: save it in a temporary register when possible) */ |