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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-12-21 16:50:26 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-12-24 08:32:15 -0800 |
| commit | e4a8e093dc74be049f4829831dce76e5edab0003 (patch) | |
| tree | 20354b9913086ac3a535e06e4d28057f88710d14 /target/xtensa/cpu.h | |
| parent | 59abfb444e1d9654e15f85c50d09a3366e4c1c1e (diff) | |
| download | focaccia-qemu-e4a8e093dc74be049f4829831dce76e5edab0003.tar.gz focaccia-qemu-e4a8e093dc74be049f4829831dce76e5edab0003.zip | |
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
Convert all targets simultaneously, as the gen_intermediate_code function disappears from the target. While there are possible workarounds, they're larger than simply performing the conversion. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/xtensa/cpu.h')
| -rw-r--r-- | target/xtensa/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 77e48eef19..0e6302c5bd 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -617,6 +617,8 @@ G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, void xtensa_collect_sr_names(const XtensaConfig *config); void xtensa_translate_init(void); +void xtensa_translate_code(CPUState *cs, TranslationBlock *tb, + int *max_insns, vaddr pc, void *host_pc); void **xtensa_get_regfile_by_name(const char *name, int entries, int bits); void xtensa_breakpoint_handler(CPUState *cs); void xtensa_register_core(XtensaConfigList *node); |