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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-20 15:02:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-20 15:02:07 +0000 |
| commit | 3d2bb5cc81ca52dcff854172625a3bb33987495c (patch) | |
| tree | 464c866b0d1337bb232669cbdb7591880926ff20 /tcg/i386/tcg-target.h | |
| parent | 61e8a923646903d76a6d952019716b417d42eedc (diff) | |
| parent | 6399ab3325b7d4f77441c8a00fa9dae98bb0ac43 (diff) | |
| download | focaccia-qemu-3d2bb5cc81ca52dcff854172625a3bb33987495c.tar.gz focaccia-qemu-3d2bb5cc81ca52dcff854172625a3bb33987495c.zip | |
Merge remote-tracking branch 'remotes/rth/tcg-next' into staging
* remotes/rth/tcg-next: tcg/i386: Use SHLX/SHRX/SARX instructions tcg/i386: Use ANDN instruction tcg/i386: Add tcg_out_vex_modrm tcg/i386: Move TCG_CT_CONST_* to tcg-target.c disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX tcg/optimize: Add more identity simplifications tcg/optimize: Optmize ANDC X,Y,Y to MOV X,0 tcg/optimize: Simply some logical ops to NOT tcg/optimize: Handle known-zeros masks for ANDC tcg/optimize: add known-zero bits compute for load ops tcg/optimize: improve known-zero bits for 32-bit ops tcg/optimize: fix known-zero bits optimization tcg/optimize: fix known-zero bits for right shift ops tcg-arm: The shift count of op_rotl_i32 is in args[2] not args[1]. TCG: Fix 32-bit host allocation typo Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/i386/tcg-target.h')
| -rw-r--r-- | tcg/i386/tcg-target.h | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 92c0fcd36d..bdf2222452 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -64,9 +64,6 @@ typedef enum { TCG_REG_RDI = TCG_REG_EDI, } TCGReg; -#define TCG_CT_CONST_S32 0x100 -#define TCG_CT_CONST_U32 0x200 - /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_ESP #define TCG_TARGET_STACK_ALIGN 16 @@ -76,6 +73,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #endif +extern bool have_bmi1; + /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 #define TCG_TARGET_HAS_rot_i32 1 @@ -87,7 +86,7 @@ typedef enum { #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_neg_i32 1 #define TCG_TARGET_HAS_not_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 +#define TCG_TARGET_HAS_andc_i32 have_bmi1 #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 @@ -115,7 +114,7 @@ typedef enum { #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_neg_i64 1 #define TCG_TARGET_HAS_not_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 +#define TCG_TARGET_HAS_andc_i64 have_bmi1 #define TCG_TARGET_HAS_orc_i64 0 #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 |