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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-02-04 18:08:19 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-02-18 07:33:42 -0800 |
| commit | 0cd38379a8f47f3bbfb0b0c8419a7de28f8c9b8c (patch) | |
| tree | 51fce3042ceb6ae228c0430242780c1fcafd4d0b /tcg/mips/tcg-target.c.inc | |
| parent | 7a967f34660c06f8d304fecd118f046fe21cb261 (diff) | |
| download | focaccia-qemu-0cd38379a8f47f3bbfb0b0c8419a7de28f8c9b8c.tar.gz focaccia-qemu-0cd38379a8f47f3bbfb0b0c8419a7de28f8c9b8c.zip | |
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
There is now always only one guest address register. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/mips/tcg-target.c.inc')
| -rw-r--r-- | tcg/mips/tcg-target.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 153ce1f3c3..d744b853cd 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1244,7 +1244,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ldst = new_ldst_label(s); ldst->is_ld = is_ld; ldst->oi = oi; - ldst->addrlo_reg = addr; + ldst->addr_reg = addr; /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); @@ -1309,7 +1309,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ldst->is_ld = is_ld; ldst->oi = oi; - ldst->addrlo_reg = addr; + ldst->addr_reg = addr; /* We are expecting a_bits to max out at 7, much lower than ANDI. */ tcg_debug_assert(a_bits < 16); |