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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-12-09 13:57:09 -0600 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-12-24 08:32:15 -0800 |
| commit | a3a88b17c2b2f682554a113e87e764c516e93e08 (patch) | |
| tree | bffc1f6868caa4039d2194fd67eb8943e3178281 /tcg/optimize.c | |
| parent | 0ae564288947d3670aaa75c931e838d5265d2a64 (diff) | |
| download | focaccia-qemu-a3a88b17c2b2f682554a113e87e764c516e93e08.tar.gz focaccia-qemu-a3a88b17c2b2f682554a113e87e764c516e93e08.zip | |
tcg/optimize: Remove z_mask, s_mask from OptContext
All mask setting is now done with parameters via fold_masks_*. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/optimize.c')
| -rw-r--r-- | tcg/optimize.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/tcg/optimize.c b/tcg/optimize.c index 51cfcb15d2..98b41975af 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -64,8 +64,6 @@ typedef struct OptContext { QSIMPLEQ_HEAD(, MemCopyInfo) mem_free; /* In flight values from optimization. */ - uint64_t z_mask; /* mask bit is 0 iff value bit is 0 */ - uint64_t s_mask; /* mask bit is 1 if value bit matches msb */ TCGType type; } OptContext; @@ -961,13 +959,6 @@ static bool finish_folding(OptContext *ctx, TCGOp *op) for (i = 0; i < nb_oargs; i++) { TCGTemp *ts = arg_temp(op->args[i]); reset_ts(ctx, ts); - /* - * Save the corresponding known-zero/sign bits mask for the - * first output argument (only one supported so far). - */ - if (i == 0) { - ts_info(ts)->z_mask = ctx->z_mask; - } } return true; } @@ -2879,10 +2870,6 @@ void tcg_optimize(TCGContext *s) ctx.type = TCG_TYPE_I32; } - /* Assume all bits affected, no bits known zero, no sign reps. */ - ctx.z_mask = -1; - ctx.s_mask = 0; - /* * Process each opcode. * Sorted alphabetically by opcode as much as possible. |