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authorRichard Henderson <richard.henderson@linaro.org>2025-01-07 14:10:27 -0800
committerRichard Henderson <richard.henderson@linaro.org>2025-04-28 13:40:16 -0700
commit6d1a2365eaee0603347fd2fabd89a8dc935c8ac7 (patch)
tree39060c47da9e7654a66d5d1964deaab718842cd1 /tcg/riscv/tcg-target-has.h
parentb2c514f9d5cab89814dc8a6b7c98c653ca8523d3 (diff)
downloadfocaccia-qemu-6d1a2365eaee0603347fd2fabd89a8dc935c8ac7.tar.gz
focaccia-qemu-6d1a2365eaee0603347fd2fabd89a8dc935c8ac7.zip
tcg: Convert divu to TCGOutOpBinary
For TCI, we're losing type information in the interpreter.
Introduce a tci-specific opcode to handle the difference.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv/tcg-target-has.h')
-rw-r--r--tcg/riscv/tcg-target-has.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
index f7e1ef82fc..ae6624b9a4 100644
--- a/tcg/riscv/tcg-target-has.h
+++ b/tcg/riscv/tcg-target-has.h
@@ -11,7 +11,6 @@
 
 /* optional instructions */
 #define TCG_TARGET_HAS_negsetcond_i32   1
-#define TCG_TARGET_HAS_div_i32          1
 #define TCG_TARGET_HAS_rem_i32          1
 #define TCG_TARGET_HAS_div2_i32         0
 #define TCG_TARGET_HAS_rot_i32          (cpuinfo & CPUINFO_ZBB)
@@ -28,7 +27,6 @@
 #define TCG_TARGET_HAS_qemu_st8_i32     0
 
 #define TCG_TARGET_HAS_negsetcond_i64   1
-#define TCG_TARGET_HAS_div_i64          1
 #define TCG_TARGET_HAS_rem_i64          1
 #define TCG_TARGET_HAS_div2_i64         0
 #define TCG_TARGET_HAS_rot_i64          (cpuinfo & CPUINFO_ZBB)