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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-03-22 13:52:09 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-06-10 07:03:34 -0700 |
| commit | a40ec84ee2b02086e27fab78a152c20b09c723cf (patch) | |
| tree | cf5efed68e90ae2240ecf558eddb0e18d890e275 /tcg/riscv/tcg-target.inc.c | |
| parent | 74433bf083b0766aba81534f92de13194f23ff3e (diff) | |
| download | focaccia-qemu-a40ec84ee2b02086e27fab78a152c20b09c723cf.tar.gz focaccia-qemu-a40ec84ee2b02086e27fab78a152c20b09c723cf.zip | |
tcg: Create struct CPUTLB
Move all softmmu tlb data into this structure. Arrange the members so that we are able to place mask+table together and at a smaller absolute offset from ENV. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv/tcg-target.inc.c')
| -rw-r--r-- | tcg/riscv/tcg-target.inc.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 6497a4dab2..96c33bf621 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -962,14 +962,6 @@ static void * const qemu_st_helpers[16] = { /* We don't support oversize guests */ QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - -/* We expect tlb_mask to be "near" tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) - - offsetof(CPUArchState, tlb_mask) >= 0x800); - static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) @@ -982,8 +974,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, int mask_off, table_off; TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; - mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); - table_off = offsetof(CPUArchState, tlb_table[mem_index]); + mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); + table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); if (table_off > 0x7ff) { int mask_hi = mask_off - sextreg(mask_off, 0, 12); int table_hi = table_off - sextreg(table_off, 0, 12); |