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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-06-10 16:09:19 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-06-10 16:09:19 +0100 |
| commit | a578cdfbdd8f9beff5ced52b7826ddb1669abbbf (patch) | |
| tree | 90697278e6aefd0b91858c403ddb5670f6bdf053 /tcg/s390/tcg-target.inc.c | |
| parent | 19735c837ae2056b4651720290eda59498eca65a (diff) | |
| parent | 43b3952dea0f763ceeaa2f119c473b5cc6d29c90 (diff) | |
| download | focaccia-qemu-a578cdfbdd8f9beff5ced52b7826ddb1669abbbf.tar.gz focaccia-qemu-a578cdfbdd8f9beff5ced52b7826ddb1669abbbf.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190610' into staging
Move softmmu tlb into CPUNegativeOffsetState # gpg: Signature made Mon 10 Jun 2019 15:07:55 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190610: (39 commits) tcg/arm: Remove mostly unreachable tlb special case tcg/arm: Use LDRD to load tlb mask+table tcg/aarch64: Use LDP to load tlb mask+table cpu: Remove CPU_COMMON cpu: Move the softmmu tlb to CPUNegativeOffsetState cpu: Move icount_decr to CPUNegativeOffsetState cpu: Introduce CPUNegativeOffsetState cpu: Introduce cpu_set_cpustate_pointers cpu: Move ENV_OFFSET to exec/gen-icount.h target/xtensa: Use env_cpu, env_archcpu target/unicore32: Use env_cpu, env_archcpu target/tricore: Use env_cpu target/tilegx: Use env_cpu target/sparc: Use env_cpu, env_archcpu target/sh4: Use env_cpu, env_archcpu target/s390x: Use env_cpu, env_archcpu target/riscv: Use env_cpu, env_archcpu target/ppc: Use env_cpu, env_archcpu target/openrisc: Use env_cpu, env_archcpu target/nios2: Use env_cpu, env_archcpu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/s390/tcg-target.inc.c')
| -rw-r--r-- | tcg/s390/tcg-target.inc.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 331d51852c..fe42939d98 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1538,11 +1538,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data, #if defined(CONFIG_SOFTMMU) #include "tcg-ldst.inc.c" -/* We're expecting to use a 20-bit signed offset on the tlb memory ops. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_mask[NB_MMU_MODES - 1]) - > 0x7ffff); -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1]) - > 0x7ffff); +/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); +QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); /* Load and compare a TLB entry, leaving the flags set. Loads the TLB addend into R2. Returns a register with the santitized guest address. */ @@ -1553,8 +1551,9 @@ static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc, unsigned a_bits = get_alignment_bits(opc); unsigned s_mask = (1 << s_bits) - 1; unsigned a_mask = (1 << a_bits) - 1; - int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off = offsetof(CPUArchState, tlb_table[mem_index]); + int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); + int table_off = fast_off + offsetof(CPUTLBDescFast, table); int ofs, a_off; uint64_t tlb_mask; |