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authorRichard Henderson <richard.henderson@linaro.org>2025-01-09 08:59:52 -0800
committerRichard Henderson <richard.henderson@linaro.org>2025-04-28 13:40:16 -0700
commitd37bc370fcad08698e4b6de99184361a2cf71ac0 (patch)
tree1e7609416c8a0c8317be8a112533e246e35010ce /tcg/tcg.c
parentbfe964809bf6ce951b2e674929d7b730c754e298 (diff)
downloadfocaccia-qemu-d37bc370fcad08698e4b6de99184361a2cf71ac0.tar.gz
focaccia-qemu-d37bc370fcad08698e4b6de99184361a2cf71ac0.zip
tcg: Convert mulu2 to TCGOutOpMul2
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tcg.c')
-rw-r--r--tcg/tcg.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5b22c75d2e..d38b55d04f 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1043,6 +1043,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
     OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
     OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2),
     OUTOP(INDEX_op_mulsh, TCGOutOpBinary, outop_mulsh),
+    OUTOP(INDEX_op_mulu2_i32, TCGOutOpMul2, outop_mulu2),
+    OUTOP(INDEX_op_mulu2_i64, TCGOutOpMul2, outop_mulu2),
     OUTOP(INDEX_op_muluh, TCGOutOpBinary, outop_muluh),
     OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
     OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg),
@@ -2290,8 +2292,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
         return TCG_TARGET_HAS_add2_i32;
     case INDEX_op_sub2_i32:
         return TCG_TARGET_HAS_sub2_i32;
-    case INDEX_op_mulu2_i32:
-        return TCG_TARGET_HAS_mulu2_i32;
     case INDEX_op_bswap16_i32:
         return TCG_TARGET_HAS_bswap16_i32;
     case INDEX_op_bswap32_i32:
@@ -2339,8 +2339,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
         return TCG_TARGET_HAS_add2_i64;
     case INDEX_op_sub2_i64:
         return TCG_TARGET_HAS_sub2_i64;
-    case INDEX_op_mulu2_i64:
-        return TCG_TARGET_HAS_mulu2_i64;
 
     case INDEX_op_mov_vec:
     case INDEX_op_dup_vec:
@@ -5476,6 +5474,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
         break;
 
     case INDEX_op_muls2:
+    case INDEX_op_mulu2_i32:
+    case INDEX_op_mulu2_i64:
         {
             const TCGOutOpMul2 *out =
                 container_of(all_outop[op->opc], TCGOutOpMul2, base);