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authorAurelien Jarno <aurelien@aurel32.net>2015-07-27 12:41:45 +0200
committerRichard Henderson <rth@twiddle.net>2015-08-24 11:10:54 -0700
commit4f2331e5b67af8172419eb1c8db510b497b30a7b (patch)
treef75277a941aedca7d786198de56e2083e376bf11 /tci.c
parent6acd2558fdb7dd9de6b10697914bdc1d75d624e5 (diff)
downloadfocaccia-qemu-4f2331e5b67af8172419eb1c8db510b497b30a7b.tar.gz
focaccia-qemu-4f2331e5b67af8172419eb1c8db510b497b30a7b.zip
tcg: implement real ext_i32_i64 and extu_i32_i64 ops
Implement real ext_i32_i64 and extu_i32_i64 ops. They ensure that a
32-bit value is always converted to a 64-bit value and not propagated
through the register allocator or the optimizer.

Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Stefan Weil <sw@weilnetz.de>
Acked-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tci.c')
-rw-r--r--tci.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/tci.c b/tci.c
index 84449489d2..3d6d17783d 100644
--- a/tci.c
+++ b/tci.c
@@ -1033,18 +1033,20 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
 #endif
 #if TCG_TARGET_HAS_ext32s_i64
         case INDEX_op_ext32s_i64:
+#endif
+        case INDEX_op_ext_i32_i64:
             t0 = *tb_ptr++;
             t1 = tci_read_r32s(&tb_ptr);
             tci_write_reg64(t0, t1);
             break;
-#endif
 #if TCG_TARGET_HAS_ext32u_i64
         case INDEX_op_ext32u_i64:
+#endif
+        case INDEX_op_extu_i32_i64:
             t0 = *tb_ptr++;
             t1 = tci_read_r32(&tb_ptr);
             tci_write_reg64(t0, t1);
             break;
-#endif
 #if TCG_TARGET_HAS_bswap16_i64
         case INDEX_op_bswap16_i64:
             TODO();