diff options
| -rw-r--r-- | target/tricore/cpu.h | 7 | ||||
| -rw-r--r-- | target/tricore/csfr.def | 1 | ||||
| -rw-r--r-- | target/tricore/op_helper.c | 29 | ||||
| -rw-r--r-- | target/tricore/translate.c | 31 | ||||
| -rw-r--r-- | target/tricore/tricore-opcodes.h | 3 |
5 files changed, 53 insertions, 18 deletions
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index e7dfe4bcc6..07b8b59f58 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -58,6 +58,7 @@ struct CPUTriCoreState { uint32_t PC; uint32_t SYSCON; uint32_t CPU_ID; + uint32_t CORE_ID; uint32_t BIV; uint32_t BTV; uint32_t ISP; @@ -228,7 +229,8 @@ void tricore_cpu_dump_state(CPUState *cpu, FILE *f, #define MASK_PCXI_PCPN 0xff000000 -#define MASK_PCXI_PIE 0x00800000 +#define MASK_PCXI_PIE_1_3 0x00800000 +#define MASK_PCXI_PIE_1_6 0x00200000 #define MASK_PCXI_UL 0x00400000 #define MASK_PCXI_PCXS 0x000f0000 #define MASK_PCXI_PCXO 0x0000ffff @@ -255,7 +257,8 @@ void tricore_cpu_dump_state(CPUState *cpu, FILE *f, #define MASK_CPUID_REV 0x000000ff #define MASK_ICR_PIPN 0x00ff0000 -#define MASK_ICR_IE 0x00000100 +#define MASK_ICR_IE_1_3 0x00000100 +#define MASK_ICR_IE_1_6 0x00008000 #define MASK_ICR_CCPN 0x000000ff #define MASK_FCX_FCXS 0x000f0000 diff --git a/target/tricore/csfr.def b/target/tricore/csfr.def index 05c45dd628..ff004cbddc 100644 --- a/target/tricore/csfr.def +++ b/target/tricore/csfr.def @@ -10,6 +10,7 @@ A(0xfe00, PCXI, TRICORE_FEATURE_13) A(0xfe08, PC, TRICORE_FEATURE_13) A(0xfe14, SYSCON, TRICORE_FEATURE_13) R(0xfe18, CPU_ID, TRICORE_FEATURE_13) +R(0xfe1c, CORE_ID, TRICORE_FEATURE_161) E(0xfe20, BIV, TRICORE_FEATURE_13) E(0xfe24, BTV, TRICORE_FEATURE_13) E(0xfe28, ISP, TRICORE_FEATURE_13) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 098f217c2a..16955f273e 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -84,8 +84,8 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin, ICR.IE and ICR.CCPN are saved */ /* PCXI.PIE = ICR.IE */ - env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) + + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.PCPN = ICR.CCPN */ env->PCXI = (env->PCXI & 0xffffff) + ((env->ICR & MASK_ICR_CCPN) << 24); @@ -2464,8 +2464,8 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc) env->PCXI = (env->PCXI & 0xffffff) + ((env->ICR & MASK_ICR_CCPN) << 24); /* PCXI.PIE = ICR.IE; */ - env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) + + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.UL = 1; */ env->PCXI |= MASK_PCXI_UL; @@ -2562,8 +2562,8 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9) env->PCXI = (env->PCXI & 0xffffff) + ((env->ICR & MASK_ICR_CCPN) << 24); /* PCXI.PIE = ICR.IE */ - env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) + + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.UL = 0 */ env->PCXI &= ~(MASK_PCXI_UL); /* PCXI[19: 0] = FCX[19: 0] */ @@ -2571,7 +2571,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9) /* FXC[19: 0] = new_FCX[19: 0] */ env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff); /* ICR.IE = 1 */ - env->ICR |= MASK_ICR_IE; + env->ICR |= MASK_ICR_IE_1_3; env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/ @@ -2603,7 +2603,8 @@ void helper_rfe(CPUTriCoreState *env) } env->PC = env->gpr_a[11] & ~0x1; /* ICR.IE = PCXI.PIE; */ - env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15); + env->ICR = (env->ICR & ~MASK_ICR_IE_1_3) + + ((env->PCXI & MASK_PCXI_PIE_1_3) >> 15); /* ICR.CCPN = PCXI.PCPN; */ env->ICR = (env->ICR & ~MASK_ICR_CCPN) + ((env->PCXI & MASK_PCXI_PCPN) >> 24); @@ -2627,8 +2628,8 @@ void helper_rfm(CPUTriCoreState *env) { env->PC = (env->gpr_a[11] & ~0x1); /* ICR.IE = PCXI.PIE; */ - env->ICR = (env->ICR & ~MASK_ICR_IE) | - ((env->PCXI & MASK_PCXI_PIE) >> 15); + env->ICR = (env->ICR & ~MASK_ICR_IE_1_3) + | ((env->PCXI & MASK_PCXI_PIE_1_3) >> 15); /* ICR.CCPN = PCXI.PCPN; */ env->ICR = (env->ICR & ~MASK_ICR_CCPN) | ((env->PCXI & MASK_PCXI_PCPN) >> 24); @@ -2693,8 +2694,8 @@ void helper_svlcx(CPUTriCoreState *env) env->PCXI = (env->PCXI & 0xffffff) + ((env->ICR & MASK_ICR_CCPN) << 24); /* PCXI.PIE = ICR.IE; */ - env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) + + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.UL = 0; */ env->PCXI &= ~MASK_PCXI_UL; @@ -2736,8 +2737,8 @@ void helper_svucx(CPUTriCoreState *env) env->PCXI = (env->PCXI & 0xffffff) + ((env->ICR & MASK_ICR_CCPN) << 24); /* PCXI.PIE = ICR.IE; */ - env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) + + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.UL = 1; */ env->PCXI |= MASK_PCXI_UL; diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 4e5b083665..aef0d9cf06 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -3389,10 +3389,18 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], offset); break; + case OPC1_16_SBR_JEQ2: + gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], + offset + 16); + break; case OPC1_16_SBR_JNE: gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], offset); break; + case OPC1_16_SBR_JNE2: + gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], + offset + 16); + break; case OPC1_16_SBR_JNZ: gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); break; @@ -4121,6 +4129,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) gen_compute_branch(ctx, op1, 0, 0, const16, address); break; /* SBR-format */ + case OPC1_16_SBR_JEQ2: + case OPC1_16_SBR_JNE2: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + r1 = MASK_OP_SBR_S2(ctx->opcode); + address = MASK_OP_SBR_DISP4(ctx->opcode); + gen_compute_branch(ctx, op1, r1, 0, 0, address); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } + break; case OPC1_16_SBR_JEQ: case OPC1_16_SBR_JGEZ: case OPC1_16_SBR_JGTZ: @@ -6256,6 +6274,15 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } break; + case OPC2_32_RR_MOVS_64: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + CHECK_REG_PAIR(r3); + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); + tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } + break; case OPC2_32_RR_NE: tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); @@ -8352,12 +8379,12 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) /* raise EXCP_DEBUG */ break; case OPC2_32_SYS_DISABLE: - tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE); + tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); break; case OPC2_32_SYS_DSYNC: break; case OPC2_32_SYS_ENABLE: - tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE); + tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3); break; case OPC2_32_SYS_ISYNC: break; diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h index 08394b85ac..2c3baab694 100644 --- a/target/tricore/tricore-opcodes.h +++ b/target/tricore/tricore-opcodes.h @@ -313,6 +313,7 @@ enum { OPC1_16_SBC_JEQ = 0x1e, OPC1_16_SBC_JEQ2 = 0x9e, OPC1_16_SBR_JEQ = 0x3e, + OPC1_16_SBR_JEQ2 = 0xbe, OPC1_16_SBR_JGEZ = 0xce, OPC1_16_SBR_JGTZ = 0x4e, OPC1_16_SR_JI = 0xdc, @@ -321,6 +322,7 @@ enum { OPC1_16_SBC_JNE = 0x5e, OPC1_16_SBC_JNE2 = 0xde, OPC1_16_SBR_JNE = 0x7e, + OPC1_16_SBR_JNE2 = 0xfe, OPC1_16_SB_JNZ = 0xee, OPC1_16_SBR_JNZ = 0xf6, OPC1_16_SBR_JNZ_A = 0x7c, @@ -1064,6 +1066,7 @@ enum { OPC2_32_RR_MIN_H = 0x78, OPC2_32_RR_MIN_HU = 0x79, OPC2_32_RR_MOV = 0x1f, + OPC2_32_RR_MOVS_64 = 0x80, OPC2_32_RR_MOV_64 = 0x81, OPC2_32_RR_NE = 0x11, OPC2_32_RR_OR_EQ = 0x27, |